[PATCH] Fix wrong code generation for AMD Fam 11h CPUs in 32-bit mode
mikpe at it.uu.se
Tue Mar 6 15:02:35 CET 2012
Torbjorn Granlund writes:
> Thanks for a model bug report!
> This is clearly a bug in GMP's config.guess.
> Do you have any idea about how common this "K8.5" CPU core might be? I
> had completely missed its existence. Were they only ever marketed as
> "Turion", and only a fraction of the Turions used this core?
I suspect Fam 11h is somewhat common. According to the Fam 11h revision
guide there are Athlons, Semprons, and Turions based on it, in both single
and dual-core configurarions (Turions only as dual-core). I see no signs
of any Opterons being based on it though.
Turions have also been based on the older Fam 0Fh, and on the newer Fam 10h.
> I am quite surprised by the nature of the 'make check' failures; if the
> compiler is directed by GMP to use unimplemented instructions, I'd
> really expect "Illegal instruction" traps, not miscomputations,
> segfaults, and hangs!
> And in 64-bit mode all works fine. Even more strange.
Yes, I would have expected SIGILLs, but got none. I even checked the first
10 or so core dumps, but apart from the first (explicit assert) they SEGVd
in plain integer code free of any fancy new instructions.
> If you copy some of the failing GMP test cases to a K10 machine, do tey
> work fine?
Yes, the binaries work fine on an Opteron 2427 (family 10h model 8).
P.S. Erik Hagersten just walked by and asked me to say Hi from him :-)
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