[PATCH] T3/T4 sparc shifts, plus more timings

David Miller davem at davemloft.net
Sun Mar 31 06:02:21 CEST 2013

From: David Miller <davem at davemloft.net>
Date: Sat, 30 Mar 2013 23:48:23 -0400 (EDT)

> From: Torbjorn Granlund <tg at gmplib.org>
> Date: Sun, 31 Mar 2013 05:03:10 +0200
>> Perhaps you could look into that?
> The fundamental issue appears to be that the chip won't schedule the
> instruction that updates "n" along with any instruction that uses "n"
> as an input (which are all the memory operations, which must issue
> every cycle for this perfect scheduling to work).  Even if we put the
> 'n' update later in the instruction group than the referencing
> instruction.

Actually, this can't be true... I've schedule code like this tons
of times.

> I actually don't have a pre-UltraSPARC-III system powered on and at
> hand at the moment to toy with that scheduling issue, I only tested on
> an UltraSPARC-IIIi.

I think this aspect of the pipeline is the same between pre-III chips
and III/IV chips.  So I can play around with this actually.

The only major difference in the pipeline for integer code going from
pre-III to III is that the integer pipelines are fully symmetric (so
you can issue two shifts per cycle).

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