[PATCH] T3/T4 sparc shifts, plus more timings
davem at davemloft.net
Sun Mar 31 05:48:23 CEST 2013
From: Torbjorn Granlund <tg at gmplib.org>
Date: Sun, 31 Mar 2013 05:03:10 +0200
> Perhaps you could look into that?
The fundamental issue appears to be that the chip won't schedule the
instruction that updates "n" along with any instruction that uses "n"
as an input (which are all the memory operations, which must issue
every cycle for this perfect scheduling to work). Even if we put the
'n' update later in the instruction group than the referencing
I actually don't have a pre-UltraSPARC-III system powered on and at
hand at the moment to toy with that scheduling issue, I only tested on
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