Runs generic code version on VIA processors

[Agner Fog]

Torbjorn Granlund wrote:
>     Which fat.c?  Are you talking about mpn/x86/fat/fat.c or
>     mpn/x86_64/fat/fat.c?
>   
>   both
>   
> I've checked in a much better mpn/x86_64/fat/fat.c.
>
>   Just look at the code. It checks family and model numbers, not feature
>   bits. You cannot make any assumptions about which instruction set is
>   supported by an unknown processor based on the family and model numbers.
>   
> OK, so you are talking about a hypothetical problem, not one actually
> triggered by any current processor.
>
> I agree that Intel might launch a new P6 family processor without, say,
> SSE2 and MMX but with a large model number.  Then GMP will crash for
> this processor.
>
> (I prefer to work with real problems than with hypothetical problems.)
>   
I would rather be safe than sorry. There is a strong trend towards new 
low-power processors with reduced complexity. You may optimize the next 
version of GMP for the new AVX instruction set on processor model X, and 
see it crash on model X+1 that has no AVX. It is too late to fix the 
problem when an application crashes.
>   The feature bits for instruction sets will always be correct. The family
>   and model numbers contain no useful information in this respect.
>   
> Which exact virtualisation system does this?  I'd suggest that these
> systems are the ones that need fixing.
>   
You have to program for the future, not the present. As I said before: 
It takes years from you put something in a software library till it runs 
in some software on the end-user's computer. And it takes years before a 
bug-fix makes its way into e.g. Mathematica.
>   You are not using the later instruction sets. Most of it is MMX only.
>   
> This is untrue.
>
>   You should distinguish by vendor string only when there is a significant
>   performance advantage. There may be a difference between Intel and AMD in
>   the case of a partial flags stall (that is the situation when you rely on
>   the carry flag being unchanged by INC and DEC instructions). Otherwise,
>   there will be very little advantage in distinguishing between CPU brands.
>
> You are misguided.
>   
Have you seen my optimization manuals? www.agner.org/optimize
If my manuals are misguided, please tell me
> In some situations, using the feature bits might be sufficient, but in
> GMP we optimise for processor pipelines, not merely available
> instructions.
>   
You are not checking the feature bits at all. That's bad programming 
practice.
> I suppose we could have some feature bit based fallback for unknown
> processors, but it is not clear if that would give any benefit except in
> rare situations.
>   
Running on a VIA processor is not a rare situation. They are becoming 
quite popular in notebooks.
Running on a processor that was unknown at the time the actual version 
of GMP was last updated is certainly not a rare situation. It is 
probably the majority of cases.