Runs generic code version on VIA processors
tg at gmplib.org
Sun Aug 8 20:23:50 CEST 2010
Which fat.c? Are you talking about mpn/x86/fat/fat.c or
I've checked in a much better mpn/x86_64/fat/fat.c.
Just look at the code. It checks family and model numbers, not feature
bits. You cannot make any assumptions about which instruction set is
supported by an unknown processor based on the family and model numbers.
OK, so you are talking about a hypothetical problem, not one actually
triggered by any current processor.
I agree that Intel might launch a new P6 family processor without, say,
SSE2 and MMX but with a large model number. Then GMP will crash for
(I prefer to work with real problems than with hypothetical problems.)
The feature bits for instruction sets will always be correct. The family
and model numbers contain no useful information in this respect.
Which exact virtualisation system does this? I'd suggest that these
systems are the ones that need fixing.
You are not using the later instruction sets. Most of it is MMX only.
This is untrue.
You should distinguish by vendor string only when there is a significant
performance advantage. There may be a difference between Intel and AMD in
the case of a partial flags stall (that is the situation when you rely on
the carry flag being unchanged by INC and DEC instructions). Otherwise,
there will be very little advantage in distinguishing between CPU brands.
You are misguided.
In some situations, using the feature bits might be sufficient, but in
GMP we optimise for processor pipelines, not merely available
I suppose we could have some feature bit based fallback for unknown
processors, but it is not clear if that would give any benefit except in
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