status of --enable-nails

[Anton Ertl]

On Sun, Jul 13, 2025 at 05:15:30PM +0200, Torbjörn Granlund wrote:
> I haven't followed RISC 5 as its
> ISA will never allow for competitive bignum performance.)

This is a very citable statement:-)

I have written a paper
<http://www.complang.tuwien.ac.at/anton/tmp/carry.pdf> about extending
GPRs with carry and overflow bits.  This feature would be especially
useful for an architecture that does not have carry and overflow bits,
such as RISC-V, so I give a RISC-V extension with these features as
example.

I sent the paper to several conferences, and it was rejected.  Some of
the suggestions by the reviewers would require a lot of work
(implement the extension in (simulated) hardware to show the hardware
cost, make use of the extension in a compiler to show the compiler
benefits).

But I fear that even if I would satisfy these wishes, another
objection would still prevail: How relevant is such an extension?
What proportion of CPU time is spent in multi-precision arithmentics?

If any of you has good numbers on that, the statement above might gain
some more teeth.

- anton