CPU dispatching in GMP is flawed
BlanchardJ at ieee.org
Mon Aug 9 15:32:33 CEST 2010
On Mon, Aug 9, 2010 at 10:14 AM, Agner Fog <agner at agner.org> wrote:
> Jonathan Blanchard wrote:
>> speed is just 'nice to have' but never at the price of
>> portability. (Now with a grain of salt here but still.)
> Speed can be critical in arbitrary-precision math, but I agree that the gain
> obtained by fine tuning assembly code may be relatively small. My main
> concern here is that it is not fair that the code gives "unknown" processors
> such as VIA the slow generic code, while Intel and AMD get the faster
> versions. CPU dispatching should be based on instruction sets for unknown
True that GMP is blazingly fast on my Phenom :D In case where the
build process of GMP mis-detect or can't detect the cpu it's possible
to force the architecture it will build for. Most via processor have
100% compatibility with an equivalent Intel or AMD cpu.
>> Also this
>> discussion appears to be mostly related to the way x86 cpu handles the
>> mess they created by having half a million instruction sets.
> New instruction sets are introduced for improving speed - or for fooling
> consumers into buying a new computer every year :-)
> Non-x86 architectures are adding vector instructions as well in order to
> stay competitive.
This is not really GMP directed but yes most cpu archs have vector
instructions. Some better than other, but nearly all of them have a
better backward support than SSE, for example older sparc CPU can
emulate VIS/VIS2 instruction assuming the kernel is aware of it, thus
keeping full backward compatibility.
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