Emulating a hardware signed multiplier

[Pedro Gimeno]

Torbjorn Granlund wrote:
> Sorry, my previous advice about signed long long was not very clever.
> 
>   The hardware multiplier takes two signed 64-bit numbers and produces a
>   signed 128-bit number. I'm new to GMP and I'm looking for a way to
>   make it interpret numbers the same way the hardware multiplier does.
>   
> That might be hard.  GMP stores negative numbers not in two's complement
> form, but in sign+magnitude form.  But if you generate numbers in the
> range -2^63 ... 2^63-1 then GMP and your hardware should agree on the
> result since that always fits a 128-bit two's complement number.

Since the logic functions assume two's complement, it should be easy to 
work internally with integers in that range (-2^63 through 2^63-1). Just 
precompute 2^64-1 and 2^128-1 and use them as a mask to use 'mpz_and' on 
both the operands and the result prior to sending them to the FPGA.

E.g. (not tested):

   mpz_init_set_si(a, -5);
   mpz_init_set_str(mask64, "FFFFFFFFFFFFFFFF", 16);
   mpz_init(a_fpga);

   mpz_and(a_fpga, a, mask64);
   gmp_printf("%#016ZX\n", a_fpga);

should print 0xFFFFFFFFFFFFFFFB