optimizing the cache

Paul Leyland paul at leyland.vispa.com
Wed Feb 1 23:11:07 CET 2006

On Mon, 2006-01-30 at 13:17, Torbjorn Granlund wrote:

> Not posible.
> I am not aware of any processor where you can lock data into the cache.

I am, but that claim is not very helpful since the machine in question
hasn't been sold for the last twenty years.  It was the High Level
Hardware Orion, built out of AMD 2900-series bit slice technology.

My first job in the real world was as microcoder for a small start-up in
Oxford.  I had complete control of the entire machine so could (and did)
pull some really dirty tricks with the cache, the TLB and so on.

At one point I had the fastest sieve of Erastothenes known for a given
clock speed.  I gained about a 10% speed-up by turning off the DRAM
refresh controller and relying on the program's own memory accesses to
keep the memory refreshed.  I also learned that although the data sheets
claimed that the DRAM of the day had to be refreshed every 20
microseconds or so, in reality almost all the bits would still be ok
after tens of milliseconds.   I drove several other bits of the hardware
significantly faster than the datasheets claimed was possible too.

Happy days (and truly dirty tricks).


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