IA64: non L1-hits for load operations at low-level functions (mpn_add_n)

[usenett@gmx.de]

Hi,

I have a question about the low-level functions like mpn_add_n. It seems to
me that the load-operations (in my case for ia64) are assumed to be L1-hits
with a latency of 1 clock cycle. Consider the case, where a load-operation
is a L2- or L3-hit. Could this case appear, and what for a behavior of the
function is to expect?

Regards,
Heinz