Risc V greatly underperforms

[Vincent Lefevre]

On 2021-09-20 11:53:13 +0200, Torbjorn Granlund wrote:
> Let's look at some examples of how Risc V underperforms.  First,
> addition of a double-word integer with carry-out:
> 
> 	add	t0, a4, a6	// add low words
> 	sltu	t6, t0, a4	// compute carry-out from low add
> 	add	t1, a5, a7	// add hi words
> 	sltu	t2, t1, a5	// compute carry-out from high add
> 	add	t4, t1, t6	// add carry to low result
> 	sltu	t3, t4, t1	// compute carry out from the carry add
> 	add	t6, t2, t3	// combine carries
> 
> Same for 64-bit arm:
> 
> 	adds	x12, x6, x10
> 	adcs	x13, x7, x11
> 
> Same for 64-bit x86:
> 
> 	add	%r8, %rax
> 	adc	%r9, %rdx
> (Some additional move insn might be needed for x86 due to the
> 2-operand nature of this arch.)

And even the 6502 had an ADC instruction with carry-in and carry-out.
This is the most logical and intuitive behavior, as from a hardware
point of view, the carry-in and carry-out are handled *for free*.

-- 
Vincent Lefèvre <vincent at vinc17.net> - Web: <https://www.vinc17.net/>
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