[PATCH 2/3] Add configure information for Zhaoxin processors
DylanFan-oc
DylanFan-oc at zhaoxin.com
Thu May 13 11:53:10 UTC 2021
Add configure information for zxc, kx5000 and kx6000 when using './configure --enable-fat'
configure.ac | 3 ++-
mpn/x86/fat/fat.c | 42 ++++++++++++++++++++++++++++++++++--------
mpn/x86_64/fat/fat.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++---------
3 files changed, 85 insertions(+), 18 deletions(-)
diff -r 632506b00743 configure.ac
--- a/configure.ac Sat May 08 19:34:05 2021 +0200
+++ b/configure.ac Wed May 12 15:34:23 2021 +0800
@@ -2345,7 +2345,8 @@
x86_64/k8 x86_64/k10 x86_64/bd1 x86_64/bt1 x86_64/bt2 x86_64/zen
x86_64/pentium4 x86_64/core2 x86_64/coreinhm x86_64/coreisbr
x86_64/coreihwl x86_64/coreibwl x86_64/skylake x86_64/atom
- x86_64/silvermont x86_64/goldmont x86_64/nano"
+ x86_64/silvermont x86_64/goldmont x86_64/nano
+ x86_64/zxc x86_64/kx5000 x86_64/kx6000"
fat_functions="$fat_functions addmul_2 addlsh1_n addlsh2_n sublsh1_n"
fi
diff -r 632506b00743 mpn/x86/fat/fat.c
--- a/mpn/x86/fat/fat.c Sat May 08 19:34:05 2021 +0200
+++ b/mpn/x86/fat/fat.c Wed May 12 15:34:23 2021 +0800
@@ -110,6 +110,9 @@
{ "viac3", "CentaurHauls", MAKE_FMS (6, 0) },
{ "viac32", "CentaurHauls", MAKE_FMS (6, 9) },
{ "nano", "CentaurHauls", MAKE_FMS (6, 15) },
+ { "zxc", "CentaurHauls", 0x000006FE },
+ { "kx5000", "CentaurHauls", MAKE_FMS (7, 0x1b) },
+ { "kx6000", "CentaurHauls", MAKE_FMS (7, 0x3b) },
};
static int
@@ -242,7 +245,7 @@
char vendor_string[13];
char dummy_string[12];
long fms;
- int family, model;
+ int family, model, stepping;
__gmpn_cpuid (vendor_string, 0);
vendor_string[12] = 0;
@@ -250,6 +253,7 @@
fms = __gmpn_cpuid (dummy_string, 1);
family = ((fms >> 8) & 0xf) + ((fms >> 20) & 0xff);
model = ((fms >> 4) & 0xf) + ((fms >> 12) & 0xf0);
+ stepping = (fms & 0xf);
if (strcmp (vendor_string, "GenuineIntel") == 0)
{
@@ -488,7 +492,8 @@
break;
}
}
- else if (strcmp (vendor_string, "CentaurHauls") == 0)
+ else if (strcmp (vendor_string, "CentaurHauls") == 0 ||
+ strcmp (vendor_string, " Shanghai ") == 0)
{
switch (family)
{
@@ -498,12 +503,33 @@
{
TRACE (printf (" viac32\n"));
}
- if (model >= 15)
- {
- TRACE (printf (" nano\n"));
- CPUVEC_SETUP_nano;
- }
- break;
+ if (model == 15)
+ {
+ if (stepping < 0xE)
+ {
+ TRACE(printf(" nano\n"));
+ CPUVEC_SETUP_nano;
+ }
+ else
+ {
+ TRACE (printf (" zxc\n"));
+ }
+ }
+ if (model > 15)
+ {
+ TRACE(printf(" zxc\n"));
+ }
+ break;
+ case 7:
+ if(model < 0x3B)
+ {
+ TRACE(printf(" kx5000\n"));
+ }
+ else
+ {
+ TRACE(printf(" kx6000\n"));
+ }
+ break;
}
}
else if (strcmp (vendor_string, "CyrixInstead") == 0)
diff -r 632506b00743 mpn/x86_64/fat/fat.c
--- a/mpn/x86_64/fat/fat.c Sat May 08 19:34:05 2021 +0200
+++ b/mpn/x86_64/fat/fat.c Wed May 12 15:34:23 2021 +0800
@@ -94,6 +94,10 @@
{ "zen", "AuthenticAMD", MAKE_FMS (23, 1) },
{ "nano", "CentaurHauls", MAKE_FMS (6, 15) },
+ { "zxc", "CentaurHauls", 0x000006FE },
+ { "kx5000", "CentaurHauls", MAKE_FMS (7, 0x1b) },
+ { "kx6000", "CentaurHauls", MAKE_FMS (7, 0x3b) },
+
};
static int
@@ -256,7 +260,7 @@
char vendor_string[13];
char dummy_string[12];
long fms;
- int family, model;
+ int family, model, stepping;
TRACE (printf ("__gmpn_cpuvec_init:\n"));
@@ -271,6 +275,7 @@
fms = __gmpn_cpuid (dummy_string, 1);
family = ((fms >> 8) & 0xf) + ((fms >> 20) & 0xff);
model = ((fms >> 4) & 0xf) + ((fms >> 12) & 0xf0);
+ stepping = (fms & 0xf);
/* Check extended feature flags */
__gmpn_cpuid (dummy_string, 0x80000001);
@@ -445,15 +450,50 @@
break;
}
}
- else if (strcmp (vendor_string, "CentaurHauls") == 0)
+ else if (strcmp (vendor_string, "CentaurHauls") == 0 ||
+ strcmp (vendor_string, " Shanghai ") == 0)
{
- switch (family)
- {
- case 6:
- if (model >= 15)
- CPUVEC_SETUP_nano;
- break;
- }
+ switch (family)
+ {
+ case 6:
+ if (model == 15)
+ {
+ if (stepping < 0xE)
+ {
+ TRACE(printf(" nano\n"));
+ CPUVEC_SETUP_nano;
+ }
+ else
+ {
+ TRACE (printf (" zxc\n"));
+ CPUVEC_SETUP_nano;
+ CPUVEC_SETUP_zxc;
+ }
+ }
+ if (model > 15)
+ {
+ TRACE(printf(" zxc\n"));
+ CPUVEC_SETUP_nano;
+ CPUVEC_SETUP_zxc;
+ }
+ break;
+ case 7:
+ if(model < 0x3B)
+ {
+ TRACE(printf(" kx5000\n"));
+ CPUVEC_SETUP_nano;
+ CPUVEC_SETUP_zxc;
+ CPUVEC_SETUP_kx5000;
+ }
+ else
+ {
+ TRACE(printf(" kx6000\n"));
+ CPUVEC_SETUP_nano;
+ CPUVEC_SETUP_zxc;
+ CPUVEC_SETUP_kx6000;
+ }
+ break;
+ }
}
/* There's no x86 generic mpn_preinv_divrem_1 or mpn_preinv_mod_1.
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