[PATCH] Add MIPS r6 support

Niels Möller nisse at lysator.liu.se
Fri Jun 14 17:41:41 UTC 2019

tg at gmplib.org (Torbjörn Granlund) writes:

> As you pointed out before, mipsr6 is in a way a new architecture, as r5
> code does not run on an r6, or vice versa. 

And the mips64 machine in the gcc compile farm (gcc22.fsffrance.org) is
only mips5? According to /proc/cpuinfo, two cpus described as

system type             : UBNT_E200 (CN6120p1.1-1000-NSP)
machine                 : Unknown
processor               : 0
cpu model               : Cavium Octeon II V0.1
BogoMIPS                : 2000.00
wait instruction        : yes
microsecond timers      : yes
tlb_entries             : 128
extra interrupt vector  : yes
hardware watchpoint     : yes, count: 2, address/irw mask: [0x0ffc, 0x0ffb]
isa                     : mips1 mips2 mips3 mips4 mips5 mips64r2
ASEs implemented        :
shadow register sets    : 1
kscratch registers      : 3
core                    : 0
VCED exceptions         : not available
VCEI exceptions         : not available


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