[PATCH] MIPS r6 support

YunQiang Su syq at debian.org
Fri Feb 22 05:26:53 UTC 2019


From: YunQiang Su <ysu at wavecomp.com>

MIPS r6 changes the multiply instructions:
The previous version use non-GPR for reuslt, while r6 use GPR.

The instructions are also replaced by new one:
  multu -> mulu/muhu
  dmultu -> dmulu/dmuhu

Since we need preprocessor, so the result of asm is changed
to .S from .s.
---
 mpn/m4-ccas                 |  2 +-
 mpn/mips32/addmul_1.asm     | 31 ++++++++++++++++++++++++++++++-
 mpn/mips32/mul_1.asm        | 31 +++++++++++++++++++++++++++++++
 mpn/mips32/submul_1.asm     | 31 ++++++++++++++++++++++++++++++-
 mpn/mips32/umul.asm         |  5 +++++
 mpn/mips64/addmul_1.asm     | 31 ++++++++++++++++++++++++++++++-
 mpn/mips64/mul_1.asm        | 30 ++++++++++++++++++++++++++++++
 mpn/mips64/sqr_diagonal.asm | 25 +++++++++++++++++++++++++
 mpn/mips64/submul_1.asm     | 31 ++++++++++++++++++++++++++++++-
 mpn/mips64/umul.asm         |  5 +++++
 10 files changed, 217 insertions(+), 5 deletions(-)

diff --git a/mpn/m4-ccas b/mpn/m4-ccas
index 16d80c6f5..b2204355c 100755
--- a/mpn/m4-ccas
+++ b/mpn/m4-ccas
@@ -65,7 +65,7 @@ for i in "$@"; do
         exit 1
       fi
       BASENAME=`echo "$i" | sed -e 's/\.asm$//' -e 's/^.*[\\/:]//'`
-      TMP=tmp-$BASENAME.s
+      TMP=tmp-$BASENAME.S
       ASM=$i
       CC="$CC $TMP"
       ;;
diff --git a/mpn/mips32/addmul_1.asm b/mpn/mips32/addmul_1.asm
index 9aa9e163c..eea7f4fd7 100644
--- a/mpn/mips32/addmul_1.asm
+++ b/mpn/mips32/addmul_1.asm
@@ -45,8 +45,12 @@ C feed-in phase 0
 
 C feed-in phase 1
 	addiu	$5,$5,4
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$24,$8,$7
+	muhu	$25,$8,$7
+#else
 	multu	$8,$7
-
+#endif
 	addiu	$6,$6,-1
 	beq	$6,$0,$LC0
 	 move	$2,$0		C zero cy2
@@ -56,11 +60,21 @@ C feed-in phase 1
 	lw	$8,0($5)	C load new s1 limb as early as possible
 
 Loop:	lw	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	addu	$3,$24,$0
+	addu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	addiu	$5,$5,4
 	addu	$3,$3,$2	C add old carry limb to low product limb
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$24,$8,$7
+	muhu	$25,$8,$7
+#else
 	multu	$8,$7
+#endif
 	lw	$8,0($5)	C load new s1 limb as early as possible
 	addiu	$6,$6,-1	C decrement loop counter
 	sltu	$2,$3,$2	C carry from previous addition -> $2
@@ -74,11 +88,21 @@ Loop:	lw	$10,0($4)
 
 C wind-down phase 1
 $LC1:	lw	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	addu	$3,$24,$0
+	addu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	addu	$3,$3,$2
 	sltu	$2,$3,$2
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$24,$8,$7
+	muhu	$25,$8,$7
+#else
 	multu	$8,$7
+#endif
 	addu	$3,$10,$3
 	sltu	$10,$3,$10
 	addu	$2,$2,$10
@@ -88,8 +112,13 @@ $LC1:	lw	$10,0($4)
 
 C wind-down phase 0
 $LC0:	lw	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	addu	$3,$24,$0
+	addu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	addu	$3,$3,$2
 	sltu	$2,$3,$2
 	addu	$3,$10,$3
diff --git a/mpn/mips32/mul_1.asm b/mpn/mips32/mul_1.asm
index 4337bc2bd..237664b8d 100644
--- a/mpn/mips32/mul_1.asm
+++ b/mpn/mips32/mul_1.asm
@@ -45,7 +45,12 @@ C feed-in phase 0
 
 C feed-in phase 1
 	addiu	$5,$5,4
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$25,$8,$7
+	muhu	$24,$8,$7
+#else
 	multu	$8,$7
+#endif
 
 	addiu	$6,$6,-1
 	beq	$6,$0,$LC0
@@ -55,10 +60,21 @@ C feed-in phase 1
 	beq	$6,$0,$LC1
 	lw	$8,0($5)	C load new s1 limb as early as possible
 
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+Loop:	addu	$10,$25,$0
+	addu	$9,$24,$0
+#else
 Loop:	mflo	$10
 	mfhi	$9
 	addiu	$5,$5,4
+#endif
 	addu	$10,$10,$2	C add old carry limb to low product limb
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$25,$8,$7
+	muhu	$24,$8,$7
+#else
+	multu	$8,$7
+#endif
 	multu	$8,$7
 	lw	$8,0($5)	C load new s1 limb as early as possible
 	addiu	$6,$6,-1	C decrement loop counter
@@ -69,18 +85,33 @@ Loop:	mflo	$10
 	 addu	$2,$9,$2	C add high product limb and carry from addition
 
 C wind-down phase 1
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+$LC1:	addu	$10,$25,$0
+	addu	$9,$24,$0
+#else
 $LC1:	mflo	$10
 	mfhi	$9
+#endif
 	addu	$10,$10,$2
 	sltu	$2,$10,$2
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$25,$8,$7
+	muhu	$24,$8,$7
+#else
 	multu	$8,$7
+#endif
 	sw	$10,0($4)
 	addiu	$4,$4,4
 	addu	$2,$9,$2	C add high product limb and carry from addition
 
 C wind-down phase 0
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+$LC0:	addu	$10,$25,$0
+	addu	$9,$24,$0
+#else
 $LC0:	mflo	$10
 	mfhi	$9
+#endif
 	addu	$10,$10,$2
 	sltu	$2,$10,$2
 	sw	$10,0($4)
diff --git a/mpn/mips32/submul_1.asm b/mpn/mips32/submul_1.asm
index 335722b4e..c94383241 100644
--- a/mpn/mips32/submul_1.asm
+++ b/mpn/mips32/submul_1.asm
@@ -45,8 +45,12 @@ C feed-in phase 0
 
 C feed-in phase 1
 	addiu	$5,$5,4
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$24,$8,$7
+	muhu	$25,$8,$7
+#else
 	multu	$8,$7
-
+#endif
 	addiu	$6,$6,-1
 	beq	$6,$0,$LC0
 	 move	$2,$0		C zero cy2
@@ -56,11 +60,21 @@ C feed-in phase 1
 	lw	$8,0($5)	C load new s1 limb as early as possible
 
 Loop:	lw	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	addu	$3,$24,$0
+	addu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	addiu	$5,$5,4
 	addu	$3,$3,$2	C add old carry limb to low product limb
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$24,$8,$7
+	muhu	$25,$8,$7
+#else
 	multu	$8,$7
+#endif
 	lw	$8,0($5)	C load new s1 limb as early as possible
 	addiu	$6,$6,-1	C decrement loop counter
 	sltu	$2,$3,$2	C carry from previous addition -> $2
@@ -74,11 +88,21 @@ Loop:	lw	$10,0($4)
 
 C wind-down phase 1
 $LC1:	lw	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	addu	$3,$24,$0
+	addu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	addu	$3,$3,$2
 	sltu	$2,$3,$2
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$24,$8,$7
+	muhu	$25,$8,$7
+#else
 	multu	$8,$7
+#endif
 	subu	$3,$10,$3
 	sgtu	$10,$3,$10
 	addu	$2,$2,$10
@@ -88,8 +112,13 @@ $LC1:	lw	$10,0($4)
 
 C wind-down phase 0
 $LC0:	lw	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	addu	$3,$24,$0
+	addu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	addu	$3,$3,$2
 	sltu	$2,$3,$2
 	subu	$3,$10,$3
diff --git a/mpn/mips32/umul.asm b/mpn/mips32/umul.asm
index 1ced0eb88..2a85b6bff 100644
--- a/mpn/mips32/umul.asm
+++ b/mpn/mips32/umul.asm
@@ -37,9 +37,14 @@ C v     $6
 
 ASM_START()
 PROLOGUE(mpn_umul_ppmm)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	mulu	$3,$5,$6
+	muhu	$2,$5,$6
+#else
 	multu	$5,$6
 	mflo	$3
 	mfhi	$2
+#endif
 	j	$31
 	sw	$3,0($4)
 EPILOGUE(mpn_umul_ppmm)
diff --git a/mpn/mips64/addmul_1.asm b/mpn/mips64/addmul_1.asm
index 8ff0976e2..050086b23 100644
--- a/mpn/mips64/addmul_1.asm
+++ b/mpn/mips64/addmul_1.asm
@@ -45,8 +45,12 @@ C feed-in phase 0
 
 C feed-in phase 1
 	daddiu	$5,$5,8
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$24,$8,$7
+	dmuhu	$25,$8,$7
+#else
 	dmultu	$8,$7
-
+#endif
 	daddiu	$6,$6,-1
 	beq	$6,$0,$LC0
 	 move	$2,$0		C zero cy2
@@ -56,11 +60,21 @@ C feed-in phase 1
 	ld	$8,0($5)	C load new s1 limb as early as possible
 
 Loop:	ld	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	daddu	$3,$24,$0
+	daddu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	daddiu	$5,$5,8
 	daddu	$3,$3,$2	C add old carry limb to low product limb
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$24,$8,$7
+	dmuhu	$25,$8,$7
+#else
 	dmultu	$8,$7
+#endif
 	ld	$8,0($5)	C load new s1 limb as early as possible
 	daddiu	$6,$6,-1	C decrement loop counter
 	sltu	$2,$3,$2	C carry from previous addition -> $2
@@ -74,11 +88,21 @@ Loop:	ld	$10,0($4)
 
 C wind-down phase 1
 $LC1:	ld	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	daddu	$3,$24,$0
+	daddu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	daddu	$3,$3,$2
 	sltu	$2,$3,$2
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$24,$8,$7
+	dmuhu	$25,$8,$7
+#else
 	dmultu	$8,$7
+#endif
 	daddu	$3,$10,$3
 	sltu	$10,$3,$10
 	daddu	$2,$2,$10
@@ -88,8 +112,13 @@ $LC1:	ld	$10,0($4)
 
 C wind-down phase 0
 $LC0:	ld	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	daddu	$3,$24,$0
+	daddu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	daddu	$3,$3,$2
 	sltu	$2,$3,$2
 	daddu	$3,$10,$3
diff --git a/mpn/mips64/mul_1.asm b/mpn/mips64/mul_1.asm
index 77acf0ac2..f6797d317 100644
--- a/mpn/mips64/mul_1.asm
+++ b/mpn/mips64/mul_1.asm
@@ -45,7 +45,12 @@ C feed-in phase 0
 
 C feed-in phase 1
 	daddiu	$5,$5,8
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$25,$8,$7
+	dmuhu	$24,$8,$7
+#else
 	dmultu	$8,$7
+#endif
 
 	daddiu	$6,$6,-1
 	beq	$6,$0,$LC0
@@ -56,11 +61,21 @@ C feed-in phase 1
 	ld	$8,0($5)	C load new s1 limb as early as possible
 
 Loop:	nop
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	daddu	$10,$25,$0
+	daddu	$9,$24,$0
+#else
 	mflo	$10
 	mfhi	$9
+#endif
 	daddiu	$5,$5,8
 	daddu	$10,$10,$2	C add old carry limb to low product limb
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$25,$8,$7
+	dmuhu	$24,$8,$7
+#else
 	dmultu	$8,$7
+#endif
 	ld	$8,0($5)	C load new s1 limb as early as possible
 	daddiu	$6,$6,-1	C decrement loop counter
 	sltu	$2,$10,$2	C carry from previous addition -> $2
@@ -72,18 +87,33 @@ Loop:	nop
 	 daddu	$2,$9,$2	C add high product limb and carry from addition
 
 C wind-down phase 1
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+$LC1:	daddu	$10,$25,$0
+	daddu	$9,$24,$0
+#else
 $LC1:	mflo	$10
 	mfhi	$9
+#endif
 	daddu	$10,$10,$2
 	sltu	$2,$10,$2
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$25,$8,$7
+	dmuhu	$24,$8,$7
+#else
 	dmultu	$8,$7
+#endif
 	sd	$10,0($4)
 	daddiu	$4,$4,8
 	daddu	$2,$9,$2	C add high product limb and carry from addition
 
 C wind-down phase 0
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+$LC0:	daddu	$10,$25,$0
+	daddu	$9,$24,$0
+#else
 $LC0:	mflo	$10
 	mfhi	$9
+#endif
 	daddu	$10,$10,$2
 	sltu	$2,$10,$2
 	sd	$10,0($4)
diff --git a/mpn/mips64/sqr_diagonal.asm b/mpn/mips64/sqr_diagonal.asm
index dcb87dc21..7f752d834 100644
--- a/mpn/mips64/sqr_diagonal.asm
+++ b/mpn/mips64/sqr_diagonal.asm
@@ -40,24 +40,44 @@ ASM_START()
 PROLOGUE(mpn_sqr_diagonal)
 	ld	r8,0(r5)
 	daddiu	r6,r6,-2
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	r10,r8,r8
+	dmuhu	r9,r8,r8
+#else
 	dmultu	r8,r8
+#endif
 	bltz	r6,$Lend1
 	nop
 	ld	r8,8(r5)
 	beq	r6,r0,$Lend2
 	nop
 
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+$Loop:	daddiu	r6,r6,-1
+#else
 $Loop:	mflo	r10
 	mfhi	r9
 	daddiu	r6,r6,-1
+#endif
 	sd	r10,0(r4)
 	sd	r9,8(r4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	r10,r8,r8
+	dmuhu	r9,r8,r8
+#else
 	dmultu	r8,r8
+#endif
 	ld	r8,16(r5)
 	daddiu	r5,r5,8
 	bne	r6,r0,$Loop
 	daddiu	r4,r4,16
 
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+$Lend2: sd	r10,0(r4)
+	sd	r9,8(r4)
+	dmulu	r10,r8,r8
+	dmuhu	r9,r8,r8
+#else
 $Lend2: mflo	r10
 	mfhi	r9
 	sd	r10,0(r4)
@@ -65,13 +85,18 @@ $Lend2: mflo	r10
 	dmultu	r8,r8
 	mflo	r10
 	mfhi	r9
+#endif
 	sd	r10,16(r4)
 	j	r31
 	sd	r9,24(r4)
 
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+$Lend1: sd	r10,0(r4)
+#else
 $Lend1: mflo	r10
 	mfhi	r9
 	sd	r10,0(r4)
+#endif
 	j	r31
 	sd	r9,8(r4)
 EPILOGUE(mpn_sqr_diagonal)
diff --git a/mpn/mips64/submul_1.asm b/mpn/mips64/submul_1.asm
index 089589cd7..dcb455a31 100644
--- a/mpn/mips64/submul_1.asm
+++ b/mpn/mips64/submul_1.asm
@@ -45,8 +45,12 @@ C feed-in phase 0
 
 C feed-in phase 1
 	daddiu	$5,$5,8
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$24,$8,$7
+	dmuhu	$25,$8,$7
+#else
 	dmultu	$8,$7
-
+#endif
 	daddiu	$6,$6,-1
 	beq	$6,$0,$LC0
 	 move	$2,$0		C zero cy2
@@ -56,11 +60,21 @@ C feed-in phase 1
 	ld	$8,0($5)	C load new s1 limb as early as possible
 
 Loop:	ld	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	daddu	$3,$24,$0
+	daddu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	daddiu	$5,$5,8
 	daddu	$3,$3,$2	C add old carry limb to low product limb
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$24,$8,$7
+	dmuhu	$25,$8,$7
+#else
 	dmultu	$8,$7
+#endif
 	ld	$8,0($5)	C load new s1 limb as early as possible
 	daddiu	$6,$6,-1	C decrement loop counter
 	sltu	$2,$3,$2	C carry from previous addition -> $2
@@ -74,11 +88,21 @@ Loop:	ld	$10,0($4)
 
 C wind-down phase 1
 $LC1:	ld	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	daddu	$3,$24,$0
+	daddu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	daddu	$3,$3,$2
 	sltu	$2,$3,$2
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$24,$8,$7
+	dmuhu	$25,$8,$7
+#else
 	dmultu	$8,$7
+#endif
 	dsubu	$3,$10,$3
 	sgtu	$10,$3,$10
 	daddu	$2,$2,$10
@@ -88,8 +112,13 @@ $LC1:	ld	$10,0($4)
 
 C wind-down phase 0
 $LC0:	ld	$10,0($4)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	daddu	$3,$24,$0
+	daddu	$9,$25,$0
+#else
 	mflo	$3
 	mfhi	$9
+#endif
 	daddu	$3,$3,$2
 	sltu	$2,$3,$2
 	dsubu	$3,$10,$3
diff --git a/mpn/mips64/umul.asm b/mpn/mips64/umul.asm
index b9aac5759..1ba66adb0 100644
--- a/mpn/mips64/umul.asm
+++ b/mpn/mips64/umul.asm
@@ -37,9 +37,14 @@ C v     $6
 
 ASM_START()
 PROLOGUE(mpn_umul_ppmm)
+#if defined(__mips_isa_rev) && (__mips_isa_rev>=6)
+	dmulu	$3,$5,$6
+	dmuhu	$2,$5,$6
+#else
 	dmultu	$5,$6
 	mflo	$3
 	mfhi	$2
+#endif
 	j	$31
 	sd	$3,0($4)
 EPILOGUE(mpn_umul_ppmm)
-- 
2.20.1



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