Victor Shoup shoup at cs.nyu.edu
Sun Oct 11 17:28:41 UTC 2015

Within the next couple of years, we can expect to see
a new instruction on Intel chips: VPMADD52.
This will be a part of the AVX512 ISA, but it's not clear
when actually chips with these instructions will ship.

One variant does an 8-way 52-bit x 52-bit -> low 52-bits
"fused multiply add" on integers. Another does the same,
but with the high-order 52-bits of the product.
Obviously, Intel is going to leverage their SIMD FP hardware 
for this...and one might also infer from this that true 64-bit
SIMD instructions are nowhere on Intel's roadmap.

So the question is: what is GMP's roadmap for SIMD development,
and does it include any plans for VPMADD52?  I've been talking to a
fellow at Intel about this (Shay Gueron), who is potentially interested 
in contributing code to GMP.  I'm also interested, because of potential applications 
to my NTL library for faster multi-modular FFTs.

One concrete issue: if one wanted to fully exploit VPMADD52 instructions,
then perhaps that would be a good reason to enable the "nails" feature
in GMP.


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