Memory barrier for fat initialization

[Niels Möller]

tg at gmplib.org (Torbjörn Granlund) writes:

> This scenario is only possible if cpu1's store sequence is seen as
> reordered by cpu0.  That's not supposed to happen, if plain instructions
> are used.  More modern architectures make no such store ordering
> guarantees.

I've tried to look in the intel architecture manual, but I can't find
any obvious place where this ordering guarantee is described.

That makes me wonder even more when mfence (or in particular, sfence) is
ever needed on x86? When using the special "non-temporal" store
instructions only? And why is it used in the linux kernel, does it use
non-temporal stores? Sorry these questions are drifting a bit off-topic.

At least it looks like the *fence instructions were introduced with sse
and sse2.

> If the dear compiler decides to initialise the cpuvec structure using
> any of these instructions, we might be screwed.

If it does that, I guess it should be bug-reported.

Regards,
/Niels

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