Adding support for R6 of MIPS architecture

Torbjörn Granlund tg at
Wed Feb 11 12:51:09 UTC 2015

Steve Ellcey <sellcey at> writes:

  > I think the old assembly code should be tweaked for r6 in a slightly
  > deeper way.  Two extra move instructions in a critical loop isn't OK.
  > The mips code you started with is seriously out-of-date, with
  > over-scheduling of load; this ought to be fixed too.
  My thought was to get a working version checked in and then make
  improvements after that.
While paperwork is handled, one may as well write a good version.  (And
if assign-future is not chosen, you need to finish the code before

I think mpn/alpha/addmul_1.asm might serve as a better starting point
than the mips64 lo/hi code.  That code is simple enough, yet OK for
pipelined in-order and out-of-order cores.
  The top-of-tree Qemu is pretty good these days, I use it for GCC
  testing, including R6 testing.
Have you been able to boot some kernel under QEMU in r6 mode?  Or are
you using user-level QEMU, passing options to QEMU with some trickery?

Please encrypt, key id 0xC8601622

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