[PATCH 3/3] Optimize 64-bit mpn_add_N and mpn_sub_N for sparc T3 and later.

[Torbjorn Granlund]

Richard Henderson <rth at twiddle.net> writes:

  For T3 and T4.  This file makes use of new instructions: addxc(cc).
  
Thanks.

  Honestly, why they didn't have a proper 64-bit with carry insn right
  from the very first v9 cpu is a mystery.

The SPARC cpu is so full of design mistakes that I am not surprised.

Consider their use of simm13 fields.  You can do "add r1,-1,r2" or "sub
r1,1,r2" for the same effect.  Except that sub can add slightly larger
numbers, and add can subtract slightly larger numbers...

Same for the logops (except that logop and logopn sovers each other
completely.

They should of course ether have applied the negation to the r1 operand,
or used an unsigned imm field.

Then we have the absense in v9 of a multiply insn giving the high part.
This is not just a problem for bignum, but makes expressions like x/3
(e.g. for x being some plain C type) very expensive.

The recent addtion of mpmul and a few dozen other instructions is a
current example of poor ISA design.

-- 
Torbjörn