[PATCH] Optimize 32-bit sparc T1 multiply routines.

[Torbjorn Granlund]

David Miller <davem at davemloft.net> writes:

  BTW I noticed the following while researching and working on this
  T4 stuff:
  
  http://download.intel.com/embedded/processor/whitepaper/327831.pdf
  
  Note that there are no subtract equivalents being added of these new
  add-with-carry instructions.
  
Yep, I know and I have complained loudly to my Intel contacts.

  I have also meanwhile spoken to some sparc chip folks and they made it
  clear that they consider having not added subxccc a mistake and a bug
  just like we do, and they will rectify this in a future cpu.
  
Explain them that insn asymmtry is almost always bad.  Look at the
really symmetric ARM, they have cmp and cmn, "subtractive" and
"additive" comparison.  With optimisations in compilers, things get
mixed up so that these are about as common.

SPARC is kind-of the antithesis of ARM, with a quickly designed
instruction set.  It is the Intel of the CISC arena...

(I love to hate things like "add r,simm,r" vs "sub r,simm,r".  I use add
with negated constant for subtraction, and sub with negated constant,
since that gives larger range.  They should of course have defined this
as r = simm + r and r = simm - r (or alternatively used an unsigned
constant here)!  The logic operations have the same problem.)

-- 
Torbjörn