[PATCH] Improve and consolidate sparc PIC assembler.
davem at davemloft.net
Mon Apr 15 19:21:29 CEST 2013
From: Torbjorn Granlund <tg at gmplib.org>
Date: Mon, 15 Apr 2013 17:13:34 +0200
> We may well put data in the text segment rather than rodata to allow for
> plainer code. (Incidentally, this same might be a bad idea of x86,
> where some processors refuse to keep a cache line in both I-cache and
> D-cache, and we might end up with a false sharing situation. That can
> happen as a result of speculative instruction prefetch, even if we align
> things to a cache line.)
On some chips, the cpu tries to keep datums from appearing in both the
L1 I-cache and D-cache. It compares the tags of the other cache when
a line is loaded, and purges from that other cache if there is a
match. This is how they handle writes into the instruction stream,
coherency via exclusion, and "flush" is basically a nop outside of
flushing the pipeline (the address is ignored).
So putting data into the instruction stream is a bad idea.
Better to put the objects into the correct sections. We know libgmp
is smaller than 2GB so a 64-bit signed (sethi + XOR) PC relative
access will work.
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