strange behaviour of mpz_jacobi

Torbjorn Granlund tg at
Mon Nov 30 12:15:00 CET 2009

Paul Zimmermann <Paul.Zimmermann at> writes:

  Do you have any explanation for this? A cache or TLB miss?
I have no idea what is causing the observed behaviour.

These operands are not very large, much smaller than the L1 cache of the
systems.  It is possible that operand alignment is the problem, since
different addresses can collide in a cache.  But the Core 2 cache is at
least 4-way associative, so this is not so likely.  AMD's L1 caches are
just 2-way associative, so we should be able to trigger the problem more
easily there.

(The good Core i7 numbers seem wrong btw.  Passing -p 1000000 to speed
makes them look more like the other numbers.  Something is broken here.)


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