[Gmp-commit] /var/hg/gmp: Get arm64 supplemental asm contraints right for adcs.

[mercurial at gmplib.org]

details:   /var/hg/gmp/rev/73d9ef70d14f
changeset: 18394:73d9ef70d14f
user:      Torbjorn Granlund <tg at gmplib.org>
date:      Wed Jul 19 11:44:37 2023 +0200
description:
Get arm64 supplemental asm contraints right for adcs.

diffstat:

 mpn/generic/div_qr_1n_pi1.c |  6 +++---
 mpn/generic/div_qr_1n_pi2.c |  2 +-
 mpn/generic/div_qr_1u_pi2.c |  5 +++--
 mpn/generic/div_qr_2.c      |  2 +-
 mpn/generic/mod_1_1.c       |  6 +++---
 5 files changed, 11 insertions(+), 10 deletions(-)

diffs (76 lines):

diff -r 8c6cc657458f -r 73d9ef70d14f mpn/generic/div_qr_1n_pi1.c
--- a/mpn/generic/div_qr_1n_pi1.c	Wed Jul 19 01:53:13 2023 +0200
+++ b/mpn/generic/div_qr_1n_pi1.c	Wed Jul 19 11:44:37 2023 +0200
@@ -142,11 +142,11 @@
 
 #if defined (__aarch64__) && W_TYPE_SIZE == 64
 #define add_mssaaaa(m, sh, sl, ah, al, bh, bl)				\
-  __asm__ (  "adds	%2, %5, %6\n\t"					\
-	     "adcs	%1, %3, %4\n\t"					\
+  __asm__ (  "adds	%2, %x5, %6\n\t"				\
+	     "adcs	%1, %x3, %x4\n\t"				\
 	     "csinv	%0, xzr, xzr, cc\n\t"				\
 	   : "=r" (m), "=r" (sh), "=&r" (sl)				\
-	   : "r" (ah), "rI" (bh), "%r" (al), "rI" (bl) __CLOBBER_CC)
+	   : "rZ" (ah), "rZ" (bh), "%rZ" (al), "rI" (bl) __CLOBBER_CC)
 #endif
 #endif /* defined (__GNUC__) */
 
diff -r 8c6cc657458f -r 73d9ef70d14f mpn/generic/div_qr_1n_pi2.c
--- a/mpn/generic/div_qr_1n_pi2.c	Wed Jul 19 01:53:13 2023 +0200
+++ b/mpn/generic/div_qr_1n_pi2.c	Wed Jul 19 11:44:37 2023 +0200
@@ -71,7 +71,7 @@
 
 #if defined (__aarch64__) && W_TYPE_SIZE == 64
 #define add_sssaaaa(s2, s1, s0, a1, a0, b1, b0)				\
-  __asm__ ("adds\t%2, %x6, %7\n\tadcs\t%1, %x4, %x5\n\tadc\t%0, %3, xzr"\
+  __asm__ ("adds\t%2, %x6, %7\n\tadcs\t%1, %x4, %x5\n\tadc\t%0, %x3, xzr"\
 	   : "=r" (s2), "=&r" (s1), "=&r" (s0)				\
 	   : "rZ" (s2), "%rZ"  (a1), "rZ" (b1), "%rZ" (a0), "rI" (b0)	\
 	     __CLOBBER_CC)
diff -r 8c6cc657458f -r 73d9ef70d14f mpn/generic/div_qr_1u_pi2.c
--- a/mpn/generic/div_qr_1u_pi2.c	Wed Jul 19 01:53:13 2023 +0200
+++ b/mpn/generic/div_qr_1u_pi2.c	Wed Jul 19 11:44:37 2023 +0200
@@ -71,9 +71,10 @@
 
 #if defined (__aarch64__) && W_TYPE_SIZE == 64
 #define add_sssaaaa(s2, s1, s0, a1, a0, b1, b0)				\
-  __asm__ ("adds\t%2, %x6, %7\n\tadcs\t%1, %x4, %x5\n\tadc\t%0, %3, xzr"\
+  __asm__ ("adds\t%2, %x6, %7\n\tadcs\t%1, %x4, %x5\n\tadc\t%0, %x3, xzr"\
 	   : "=r" (s2), "=&r" (s1), "=&r" (s0)				\
-	   : "rZ" (s2), "%rZ"  (a1), "rZ" (b1), "%rZ" (a0), "rI" (b0) __CLOBBER_CC)
+	   : "rZ" (s2), "%rZ"  (a1), "rZ" (b1), "%rZ" (a0), "rI" (b0)	\
+	     __CLOBBER_CC)
 #endif
 
 #if HAVE_HOST_CPU_FAMILY_powerpc && !defined (_LONG_LONG_LIMB)
diff -r 8c6cc657458f -r 73d9ef70d14f mpn/generic/div_qr_2.c
--- a/mpn/generic/div_qr_2.c	Wed Jul 19 01:53:13 2023 +0200
+++ b/mpn/generic/div_qr_2.c	Wed Jul 19 11:44:37 2023 +0200
@@ -76,7 +76,7 @@
 
 #if defined (__aarch64__) && W_TYPE_SIZE == 64
 #define add_sssaaaa(s2, s1, s0, a1, a0, b1, b0)				\
-  __asm__ ("adds\t%2, %x6, %7\n\tadcs\t%1, %x4, %x5\n\tadc\t%0, %3, xzr"\
+  __asm__ ("adds\t%2, %x6, %7\n\tadcs\t%1, %x4, %x5\n\tadc\t%0, %x3, xzr"\
 	   : "=r" (s2), "=&r" (s1), "=&r" (s0)				\
 	   : "rZ" (s2), "%rZ"  (a1), "rZ" (b1), "%rZ" (a0), "rI" (b0)	\
 	     __CLOBBER_CC)
diff -r 8c6cc657458f -r 73d9ef70d14f mpn/generic/mod_1_1.c
--- a/mpn/generic/mod_1_1.c	Wed Jul 19 01:53:13 2023 +0200
+++ b/mpn/generic/mod_1_1.c	Wed Jul 19 11:44:37 2023 +0200
@@ -141,11 +141,11 @@
 
 #if defined (__aarch64__) && W_TYPE_SIZE == 64
 #define add_mssaaaa(m, sh, sl, ah, al, bh, bl)				\
-  __asm__ (  "adds	%2, %5, %6\n\t"					\
-	     "adcs	%1, %3, %4\n\t"					\
+  __asm__ (  "adds	%2, %x5, %6\n\t"				\
+	     "adcs	%1, %x3, %x4\n\t"				\
 	     "csinv	%0, xzr, xzr, cc\n\t"				\
 	   : "=r" (m), "=r" (sh), "=&r" (sl)				\
-	   : "r" (ah), "rI" (bh), "%r" (al), "rI" (bl) __CLOBBER_CC)
+	   : "rZ" (ah), "rZ" (bh), "%rZ" (al), "rI" (bl) __CLOBBER_CC)
 #endif
 #endif /* defined (__GNUC__) */