[Gmp-commit] /var/hg/gmp: Recognise CPUs icelake, tigerlake, and rocketlake.
mercurial at gmplib.org
mercurial at gmplib.org
Sun May 2 07:01:16 UTC 2021
details: /var/hg/gmp/rev/e57144aeeb1e
changeset: 18212:e57144aeeb1e
user: Torbjorn Granlund <tg at gmplib.org>
date: Sun May 02 09:01:13 2021 +0200
description:
Recognise CPUs icelake, tigerlake, and rocketlake.
Clean up handling of several Intel CPUs.
diffstat:
config.guess | 9 +++++++--
config.sub | 2 +-
configure.ac | 24 ++++++++++++++++--------
3 files changed, 24 insertions(+), 11 deletions(-)
diffs (86 lines):
diff -r 92681f2490cc -r e57144aeeb1e config.guess
--- a/config.guess Fri Apr 16 16:49:02 2021 +0200
+++ b/config.guess Sun May 02 09:01:13 2021 +0200
@@ -919,8 +919,13 @@
else if (model == 0x5e) cpu_64bit = 1, cpu_avx=1, modelstr = "skylake"; /* Skylake */
else if (model == 0x5f) cpu_64bit = 1, modelstr = "goldmont"; /* Goldmont */
else if (model == 0x7a) cpu_64bit = 1, modelstr = "goldmont"; /* Goldmont Plus */
- else if (model == 0x8e) cpu_64bit = 1, cpu_avx=1, modelstr = "kabylake"; /* Kabylake Y/U */
- else if (model == 0x9e) cpu_64bit = 1, cpu_avx=1, modelstr = "kabylake"; /* Kabylake desktop */
+ else if (model == 0x7d) cpu_64bit = 1, cpu_avx=1, modelstr = "icelake"; /* Ice Lake Y */
+ else if (model == 0x7e) cpu_64bit = 1, cpu_avx=1, modelstr = "icelake"; /* Ice Lake U */
+ else if (model == 0x8c) cpu_64bit = 1, cpu_avx=1, modelstr = "tigerlake"; /* Tiger Lake U */
+ else if (model == 0x8d) cpu_64bit = 1, cpu_avx=1, modelstr = "tigerlake"; /* Tiger Lake H */
+ else if (model == 0x8e) cpu_64bit = 1, cpu_avx=1, modelstr = "kabylake"; /* Kaby Lake Y/U */
+ else if (model == 0x9e) cpu_64bit = 1, cpu_avx=1, modelstr = "kabylake"; /* Kaby Lake desktop */
+ else if (model == 0xa7) cpu_64bit = 1, cpu_avx=1, modelstr = "rocketlake"; /* Rocket Lake S */
else cpu_64bit = 1, modelstr = "nehalem"; /* default */
if (strcmp (modelstr, "haswell") == 0 ||
diff -r 92681f2490cc -r e57144aeeb1e config.sub
--- a/config.sub Fri Apr 16 16:49:02 2021 +0200
+++ b/config.sub Sun May 02 09:01:13 2021 +0200
@@ -102,7 +102,7 @@
test_cpu=ia64 ;;
pentium | pentiummmx | pentiumpro | pentium[234m] | k[567] | k6[23] | geode | athlon | viac3*)
test_cpu=i386 ;;
-athlon64 | atom | silvermont | goldmont | core2 | corei* | opteron | k[89] | k10 | bobcat | jaguar* | bulldozer* | piledriver* | steamroller* | excavator* | zen* | nano | nehalem | westmere | sandybridge* | ivybridge* | haswell* | broadwell* | skylake* | kabylake* | knightslanding)
+athlon64 | atom | silvermont | goldmont | core2 | corei* | opteron | k[89] | k10 | bobcat | jaguar* | bulldozer* | piledriver* | steamroller* | excavator* | zen* | nano | nehalem | westmere | sandybridge* | ivybridge* | haswell* | broadwell* | skylake* | kabylake* | icelake* | rocketlake* | tigerlake* | knightslanding)
test_cpu=x86_64 ;;
power[2-9] | power2sc)
test_cpu=power ;;
diff -r 92681f2490cc -r e57144aeeb1e configure.ac
--- a/configure.ac Fri Apr 16 16:49:02 2021 +0200
+++ b/configure.ac Sun May 02 09:01:13 2021 +0200
@@ -1939,35 +1939,43 @@
;;
coreisbr | coreisbrnoavx | coreiibr | coreiibrnoavx | \
sandybridge | sandybridgenoavx | ivybridge | ivybridgenoavx)
- gcc_cflags_cpu="-mtune=sandybridge -mtune=corei7 -mtune=core2 -mtune=k8"
- gcc_cflags_arch="-march=sandybridge -march=corei7 -march=core2 -march=core2~-mno-sse2 -march=k8 -march=k8~-mno-sse2"
+ gcc_cflags_cpu="-mtune=sandybridge -mtune=corei7 -mtune=core2"
+ gcc_cflags_arch="-march=sandybridge -march=corei7 -march=core2 -march=core2~-mno-sse2"
path="x86/coreisbr x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
path_64="x86_64/coreisbr x86_64/coreinhm x86_64/core2 x86_64"
;;
coreihwl | coreihwlnoavx | haswell | haswellnoavx)
- gcc_cflags_cpu="-mtune=haswell -mtune=corei7 -mtune=core2 -mtune=k8"
- gcc_cflags_arch="-march=haswell -march=corei7 -march=core2 -march=core2~-mno-sse2 -march=k8 -march=k8~-mno-sse2"
+ gcc_cflags_cpu="-mtune=haswell -mtune=corei7 -mtune=core2"
+ gcc_cflags_arch="-march=haswell -march=corei7 -march=core2 -march=core2~-mno-sse2"
path="x86/coreihwl x86/coreisbr x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
path_64="x86_64/coreihwl x86_64/coreisbr x86_64/coreinhm x86_64/core2 x86_64"
x86_have_mulx=yes
;;
coreibwl | coreibwlnoavx | broadwell | broadwellnoavx)
- gcc_cflags_cpu="-mtune=broadwell -mtune=corei7 -mtune=core2 -mtune=k8"
- gcc_cflags_arch="-march=broadwell -march=corei7 -march=core2 -march=core2~-mno-sse2 -march=k8 -march=k8~-mno-sse2"
+ gcc_cflags_cpu="-mtune=broadwell -mtune=haswell -mtune=corei7 -mtune=core2"
+ gcc_cflags_arch="-march=broadwell -march=haswell -march=corei7 -march=core2 -march=core2~-mno-sse2"
path="x86/coreihwl x86/coreisbr x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
path_64="x86_64/coreibwl x86_64/coreihwl x86_64/coreisbr x86_64/coreinhm x86_64/core2 x86_64"
# extra_functions_64="missing" # enable for bmi2/adx simulation
x86_have_mulx=yes
;;
skylake | skylakenoavx | kabylake | kabylakenoavx)
- gcc_cflags_cpu="-mtune=skylake -mtune=broadwell -mtune=corei7 -mtune=core2 -mtune=k8"
+ gcc_cflags_cpu="-mtune=skylake -mtune=broadwell -mtune=haswell -mtune=corei7 -mtune=core2"
# Don't pass -march=skylake for now as then some compilers emit AVX512.
- gcc_cflags_arch="-march=broadwell -march=corei7 -march=core2 -march=core2~-mno-sse2 -march=k8 -march=k8~-mno-sse2"
+ gcc_cflags_arch="-march=broadwell -march=haswell -march=corei7 -march=core2 -march=core2~-mno-sse2"
path="x86/coreihwl x86/coreisbr x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
path_64="x86_64/skylake x86_64/coreibwl x86_64/coreihwl x86_64/coreisbr x86_64/coreinhm x86_64/core2 x86_64"
# extra_functions_64="missing" # enable for bmi2/adx simulation
x86_have_mulx=yes
;;
+ icelake | icelakenoavx | tigerlake | tigerlakenoavx | rocketlake | rocketlakenoavx)
+ gcc_cflags_cpu="-mtune=icelake -mtune=skylake -mtune=broadwell -mtune=haswell"
+ gcc_cflags_arch="-march=icelake -march=skylake -march=broadwell -march=haswell"
+ path="x86/coreihwl x86/coreisbr x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
+ path_64="x86_64/icelake x86_64/skylake x86_64/coreibwl x86_64/coreihwl x86_64/coreisbr x86_64/coreinhm x86_64/core2 x86_64"
+ # extra_functions_64="missing" # enable for bmi2/adx simulation
+ x86_have_mulx=yes
+ ;;
atom) # in-order pipeline atom
gcc_cflags_cpu="-mtune=atom -mtune=pentium3"
gcc_cflags_arch="-march=atom -march=pentium3"
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