[Gmp-commit] /var/hg/gmp: 2 new changesets
mercurial at gmplib.org
mercurial at gmplib.org
Sun Feb 19 06:08:26 UTC 2017
details: /var/hg/gmp/rev/2b99b3973cc9
changeset: 17283:2b99b3973cc9
user: Torbjorn Granlund <tg at gmplib.org>
date: Fri Feb 17 05:03:37 2017 +0100
description:
* mpn/arm64/cora53/cnd_aors_n.asm: Moved from "..".
* mpn/arm64/xgene1/cnd_aors_n.asm: Remove file since default code performs better.
* mpn/arm64/cnd_aors_n.asm: Rewrite.
details: /var/hg/gmp/rev/814cfb09af29
changeset: 17284:814cfb09af29
user: Torbjorn Granlund <tg at gmplib.org>
date: Sun Feb 19 07:00:08 2017 +0100
description:
Write ARM64 mpn_mul_1 which runs well on A53, A57, X-Gene.
diffstat:
mpn/arm64/cnd_aors_n.asm | 74 +++++++++++++++------
mpn/arm64/cora53/cnd_aors_n.asm | 99 +++++++++++++++++++++++++++++
mpn/arm64/mul_1.asm | 135 ++++++++++++++++++++++++---------------
mpn/arm64/xgene1/cnd_aors_n.asm | 99 -----------------------------
mpn/arm64/xgene1/mul_1.asm | 99 -----------------------------
5 files changed, 233 insertions(+), 273 deletions(-)
diffs (truncated from 572 to 300 lines):
diff -r f5bf0bc5e104 -r 814cfb09af29 mpn/arm64/cnd_aors_n.asm
--- a/mpn/arm64/cnd_aors_n.asm Fri Feb 17 02:02:25 2017 +0100
+++ b/mpn/arm64/cnd_aors_n.asm Sun Feb 19 07:00:08 2017 +0100
@@ -33,9 +33,9 @@
include(`../config.m4')
C cycles/limb
-C Cortex-A53 3.5-4
-C Cortex-A57 2.25
-C X-Gene 3.5
+C Cortex-A53 3.87-4.37
+C Cortex-A57 1.75
+C X-Gene 2.0
changecom(blah)
@@ -63,37 +63,67 @@
cmp cnd, #1
sbc cnd, cnd, cnd
- CLRCY C really only needed for n = 0 (mod 4)
+ CLRCY
- tbz n, #0, L(1)
- ldr x10, [up], #8
- ldr x12, [vp], #8
- bic x6, x12, cnd
- ADDSUBC x8, x10, x6
- sub n, n, #1
- str x8, [rp], #8
- cbz n, L(rt)
+ lsr x18, n, #2
+ tbz n, #0, L(bx0)
-L(1): ldp x10, x11, [up], #16
- ldp x12, x13, [vp], #16
- sub n, n, #2
- cbz n, L(end)
+L(bx1): ldr x13, [vp]
+ ldr x11, [up]
+ bic x7, x13, cnd
+ ADDSUBC x9, x11, x7
+ str x9, [rp]
+ tbnz n, #1, L(b11)
+L(b01): cbz x18, L(rt)
+ ldp x12, x13, [vp,#8]
+ ldp x10, x11, [up,#8]
+ sub up, up, #8
+ sub vp, vp, #8
+ sub rp, rp, #24
+ b L(mid)
+
+L(b11): ldp x12, x13, [vp,#8]!
+ ldp x10, x11, [up,#8]!
+ sub rp, rp, #8
+ cbz x18, L(end)
+ b L(top)
+
+L(bx0): ldp x12, x13, [vp]
+ ldp x10, x11, [up]
+ tbnz n, #1, L(b10)
+
+L(b00): sub up, up, #16
+ sub vp, vp, #16
+ sub rp, rp, #32
+ b L(mid)
+
+L(b10): sub rp, rp, #16
+ cbz x18, L(end)
+
+ ALIGN(16)
L(top): bic x6, x12, cnd
bic x7, x13, cnd
- ldp x12, x13, [vp], #16
+ ldp x12, x13, [vp,#16]
ADDSUBC x8, x10, x6
ADDSUBC x9, x11, x7
- ldp x10, x11, [up], #16
- sub n, n, #2
- stp x8, x9, [rp], #16
- cbnz n, L(top)
+ ldp x10, x11, [up,#16]
+ stp x8, x9, [rp,#16]
+L(mid): bic x6, x12, cnd
+ bic x7, x13, cnd
+ ldp x12, x13, [vp,#32]!
+ ADDSUBC x8, x10, x6
+ ADDSUBC x9, x11, x7
+ ldp x10, x11, [up,#32]!
+ stp x8, x9, [rp,#32]!
+ sub x18, x18, #1
+ cbnz x18, L(top)
L(end): bic x6, x12, cnd
bic x7, x13, cnd
ADDSUBC x8, x10, x6
ADDSUBC x9, x11, x7
- stp x8, x9, [rp]
+ stp x8, x9, [rp,#16]
L(rt): RETVAL
ret
EPILOGUE()
diff -r f5bf0bc5e104 -r 814cfb09af29 mpn/arm64/cora53/cnd_aors_n.asm
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mpn/arm64/cora53/cnd_aors_n.asm Sun Feb 19 07:00:08 2017 +0100
@@ -0,0 +1,99 @@
+dnl ARM64 mpn_cnd_add_n, mpn_cnd_sub_n
+
+dnl Contributed to the GNU project by Torbjörn Granlund.
+
+dnl Copyright 2012, 2013, 2017 Free Software Foundation, Inc.
+
+dnl This file is part of the GNU MP Library.
+dnl
+dnl The GNU MP Library is free software; you can redistribute it and/or modify
+dnl it under the terms of either:
+dnl
+dnl * the GNU Lesser General Public License as published by the Free
+dnl Software Foundation; either version 3 of the License, or (at your
+dnl option) any later version.
+dnl
+dnl or
+dnl
+dnl * the GNU General Public License as published by the Free Software
+dnl Foundation; either version 2 of the License, or (at your option) any
+dnl later version.
+dnl
+dnl or both in parallel, as here.
+dnl
+dnl The GNU MP Library is distributed in the hope that it will be useful, but
+dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+dnl for more details.
+dnl
+dnl You should have received copies of the GNU General Public License and the
+dnl GNU Lesser General Public License along with the GNU MP Library. If not,
+dnl see https://www.gnu.org/licenses/.
+
+include(`../config.m4')
+
+C cycles/limb
+C Cortex-A53 3.5-4
+C Cortex-A57 2.25
+C X-Gene 3.5
+
+changecom(blah)
+
+define(`cnd', `x0')
+define(`rp', `x1')
+define(`up', `x2')
+define(`vp', `x3')
+define(`n', `x4')
+
+ifdef(`OPERATION_cnd_add_n', `
+ define(`ADDSUBC', adcs)
+ define(`CLRCY', `cmn xzr, xzr')
+ define(`RETVAL', `cset x0, cs')
+ define(`func', mpn_cnd_add_n)')
+ifdef(`OPERATION_cnd_sub_n', `
+ define(`ADDSUBC', sbcs)
+ define(`CLRCY', `cmp xzr, xzr')
+ define(`RETVAL', `cset x0, cc')
+ define(`func', mpn_cnd_sub_n)')
+
+MULFUNC_PROLOGUE(mpn_cnd_add_n mpn_cnd_sub_n)
+
+ASM_START()
+PROLOGUE(func)
+ cmp cnd, #1
+ sbc cnd, cnd, cnd
+
+ CLRCY C really only needed for n = 0 (mod 4)
+
+ tbz n, #0, L(1)
+ ldr x10, [up], #8
+ ldr x12, [vp], #8
+ bic x6, x12, cnd
+ ADDSUBC x8, x10, x6
+ sub n, n, #1
+ str x8, [rp], #8
+ cbz n, L(rt)
+
+L(1): ldp x10, x11, [up], #16
+ ldp x12, x13, [vp], #16
+ sub n, n, #2
+ cbz n, L(end)
+
+L(top): bic x6, x12, cnd
+ bic x7, x13, cnd
+ ldp x12, x13, [vp], #16
+ ADDSUBC x8, x10, x6
+ ADDSUBC x9, x11, x7
+ ldp x10, x11, [up], #16
+ sub n, n, #2
+ stp x8, x9, [rp], #16
+ cbnz n, L(top)
+
+L(end): bic x6, x12, cnd
+ bic x7, x13, cnd
+ ADDSUBC x8, x10, x6
+ ADDSUBC x9, x11, x7
+ stp x8, x9, [rp]
+L(rt): RETVAL
+ ret
+EPILOGUE()
diff -r f5bf0bc5e104 -r 814cfb09af29 mpn/arm64/mul_1.asm
--- a/mpn/arm64/mul_1.asm Fri Feb 17 02:02:25 2017 +0100
+++ b/mpn/arm64/mul_1.asm Sun Feb 19 07:00:08 2017 +0100
@@ -2,7 +2,7 @@
dnl Contributed to the GNU project by Torbjörn Granlund.
-dnl Copyright 2013 Free Software Foundation, Inc.
+dnl Copyright 2013, 2015, 2017 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
@@ -33,66 +33,95 @@
include(`../config.m4')
C cycles/limb
-C Cortex-A53 ?
-C Cortex-A57 ?
+C Cortex-A53 7.5-8
+C Cortex-A57 7
+C Cortex-A72
+C X-Gene 4
+
+C TODO
+C * Start first multiply earlier.
+
+changecom(blah)
define(`rp', `x0')
define(`up', `x1')
define(`n', `x2')
define(`v0', `x3')
-ASM_START()
-PROLOGUE(mpn_mul_1)
- ldr x12, [up], #8
- and x6, n, #3
- and n, n, #-4
- cbz x6, L(fi0)
- cmp x6, #2
- b.cc L(fi1)
- b.eq L(fi2)
-L(fi3): mul x8, x12, v0
- umulh x13, x12, v0
- cmn xzr, xzr
- b L(L3)
-L(fi2): mul x7, x12, v0
- umulh x5, x12, v0
- cmn xzr, xzr
- b L(L2)
-L(fi0): mul x9, x12, v0
- umulh x5, x12, v0
- sub n, n, #4
- cmn xzr, xzr
- b L(L0)
-L(fi1): mul x10, x12, v0
- umulh x13, x12, v0
- cmn xzr, xzr
- cbz n, L(end)
+PROLOGUE(mpn_mul_1c)
+ adds xzr, xzr, xzr C clear cy flag
+ b L(com)
+EPILOGUE()
-L(top): sub n, n, #4
- ldr x12, [up], #8
- mul x6, x12, v0
- umulh x5, x12, v0
- str x10, [rp], #8
- adcs x9, x6, x13
-L(L0): ldr x12, [up], #8
- mul x6, x12, v0
- umulh x13, x12, v0
- str x9, [rp] ,#8
- adcs x8, x6, x5
-L(L3): ldr x12, [up], #8
- mul x6, x12, v0
- umulh x5, x12, v0
- str x8, [rp], #8
- adcs x7, x6, x13
-L(L2): ldr x12, [up], #8
- mul x6, x12, v0
- umulh x13, x12, v0
- str x7, [rp], #8
- adcs x10, x6, x5
- cbnz n, L(top)
+PROLOGUE(mpn_mul_1)
+ adds x4, xzr, xzr C clear register and cy flag
+L(com): lsr x18, n, #2
+ tbnz n, #0, L(bx1)
-L(end): str x10, [rp]
- adc x0, x13, xzr
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