[Gmp-commit] /var/hg/gmp: 3 new changesets
mercurial at gmplib.org
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Fri Mar 25 19:33:07 UTC 2016
details: /var/hg/gmp/rev/ffb48cac4278
changeset: 17048:ffb48cac4278
user: Torbjorn Granlund <torbjorng at google.com>
date: Fri Mar 25 20:30:43 2016 +0100
description:
Prefix all arm CPUs with "arm" to accommodate our matchers.
details: /var/hg/gmp/rev/ae67e8ba054f
changeset: 17049:ae67e8ba054f
user: Torbjorn Granlund <torbjorng at google.com>
date: Fri Mar 25 20:32:19 2016 +0100
description:
New files.
details: /var/hg/gmp/rev/ba34e2818d6b
changeset: 17050:ba34e2818d6b
user: Torbjorn Granlund <torbjorng at google.com>
date: Fri Mar 25 20:33:05 2016 +0100
description:
ChangeLog
diffstat:
ChangeLog | 17 +++
config.guess | 6 +-
configure.ac | 6 +-
mpn/arm64/xgene1/aors_n.asm | 101 ++++++++++++++++++++++
mpn/arm64/xgene1/aorsmul_1.asm | 125 +++++++++++++++++++++++++++
mpn/arm64/xgene1/cnd_aors_n.asm | 100 +++++++++++++++++++++
mpn/arm64/xgene1/gmp-mparam.h | 183 ++++++++++++++++++++++++++++++++++++++++
mpn/arm64/xgene1/mul_1.asm | 99 +++++++++++++++++++++
8 files changed, 631 insertions(+), 6 deletions(-)
diffs (truncated from 702 to 300 lines):
diff -r 2fa752456dd9 -r ba34e2818d6b ChangeLog
--- a/ChangeLog Mon Mar 21 23:59:32 2016 +0100
+++ b/ChangeLog Fri Mar 25 20:33:05 2016 +0100
@@ -1,3 +1,19 @@
+2016-03-25 Torbjörn Granlund <torbjorng at google.com>
+
+ * mpn/arm64/xgene1/aors_n.asm: New file.
+ * mpn/arm64/xgene1/aorsmul_1.asm: New file.
+ * mpn/arm64/xgene1/cnd_aors_n.asm: New file.
+ * mpn/arm64/xgene1/gmp-mparam.h: New file.
+ * mpn/arm64/xgene1/mul_1.asm: New file.
+
+ * config.guess: Prefix all arm CPUs with "arm" to accommodate our
+ matchers.
+ * configure.ac (arm): Match arm CPUs consistently.
+
+2016-03-21 Torbjörn Granlund <torbjorng at google.com>
+
+ * configure.ac: Support many arm64 processors.
+
2015-03-20 Marc Glisse <marc.glisse at inria.fr>
* configure.ac (WANT_ASSEMBLY): Remove.
@@ -9,6 +25,7 @@
* config.guess (arm*): Handle big.LITTLE CPUs by extracting the
lexically largest id.
* config.guess (arm*): Add many aarch64 CPUs.
+ * config.guess (main): Corresponding changes.
* mpn/arm/v7a/cora5/gmp-mparam.h: New file.
diff -r 2fa752456dd9 -r ba34e2818d6b config.guess
--- a/config.guess Mon Mar 21 23:59:32 2016 +0100
+++ b/config.guess Fri Mar 25 20:33:05 2016 +0100
@@ -176,10 +176,10 @@
cpu_code=`sed -n 's/^CPU part.*\(0x.*\)$/\1/p' /proc/cpuinfo 2>/dev/null | sort -r | head -n 1 2>/dev/null`
cpu_implementer=`sed -n 's/^CPU implementer.*\(0x.*\)$/\1/p' /proc/cpuinfo 2>/dev/null | head -n 1 2>/dev/null`
case "${cpu_implementer}_${cpu_code}" in
- 0x53_0x001) exact_cpu=exynosm1 ;;
+ 0x53_0x001) exact_cpu=armexynosm1 ;;
0x51_0x800) exact_cpu=armcortexa57 ;;
- 0x43_0x0a1) exact_cpu=thunderx ;;
- 0x50_0x000) exact_cpu=xgene1 ;;
+ 0x43_0x0a1) exact_cpu=armthunderx ;;
+ 0x50_0x000) exact_cpu=armxgene1 ;;
esac
if test -z "$exact_cpu"; then
case "$cpu_code" in
diff -r 2fa752456dd9 -r ba34e2818d6b configure.ac
--- a/configure.ac Mon Mar 21 23:59:32 2016 +0100
+++ b/configure.ac Fri Mar 25 20:33:05 2016 +0100
@@ -700,19 +700,19 @@
gcc_cflags_arch=""
gcc_cflags_tune="-mtune=cortex-a72"
;;
- exynosm1)
+ armexynosm1)
unset CALLING_CONVENTIONS_OBJS
path="arm64"
gcc_cflags_arch=""
gcc_cflags_tune="-mtune=exynosm1"
;;
- thunderx)
+ armthunderx)
unset CALLING_CONVENTIONS_OBJS
path="arm64"
gcc_cflags_arch=""
gcc_cflags_tune="-mtune=thunderx"
;;
- xgene1)
+ armxgene1)
unset CALLING_CONVENTIONS_OBJS
path="arm64/xgene1 arm64"
gcc_cflags_arch=""
diff -r 2fa752456dd9 -r ba34e2818d6b mpn/arm64/xgene1/aors_n.asm
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mpn/arm64/xgene1/aors_n.asm Fri Mar 25 20:33:05 2016 +0100
@@ -0,0 +1,101 @@
+dnl ARM64 mpn_add_n and mpn_sub_n
+
+dnl Contributed to the GNU project by Torbjörn Granlund.
+
+dnl Copyright 2013, 2015 Free Software Foundation, Inc.
+
+dnl This file is part of the GNU MP Library.
+dnl
+dnl The GNU MP Library is free software; you can redistribute it and/or modify
+dnl it under the terms of either:
+dnl
+dnl * the GNU Lesser General Public License as published by the Free
+dnl Software Foundation; either version 3 of the License, or (at your
+dnl option) any later version.
+dnl
+dnl or
+dnl
+dnl * the GNU General Public License as published by the Free Software
+dnl Foundation; either version 2 of the License, or (at your option) any
+dnl later version.
+dnl
+dnl or both in parallel, as here.
+dnl
+dnl The GNU MP Library is distributed in the hope that it will be useful, but
+dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+dnl for more details.
+dnl
+dnl You should have received copies of the GNU General Public License and the
+dnl GNU Lesser General Public License along with the GNU MP Library. If not,
+dnl see https://www.gnu.org/licenses/.
+
+include(`../config.m4')
+
+C cycles/limb
+C Cortex-A53 ?
+C Cortex-A57 ?
+C X-Gene 2
+
+changecom(blah)
+
+define(`rp', `x0')
+define(`up', `x1')
+define(`vp', `x2')
+define(`n', `x3')
+
+ifdef(`OPERATION_add_n', `
+ define(`ADDSUBC', adcs)
+ define(`CLRCY', `cmn xzr, xzr')
+ define(`SETCY', `cmp $1, #1')
+ define(`RETVAL', `adc x0, xzr, xzr')
+ define(`func', mpn_add_n)
+ define(`func_nc', mpn_add_nc)')
+ifdef(`OPERATION_sub_n', `
+ define(`ADDSUBC', sbcs)
+ define(`CLRCY', `cmp xzr, xzr')
+ define(`SETCY', `subs $1, xzr, $1')
+ define(`RETVAL', `sbc x0, xzr, xzr
+ and x0, x0, #1')
+ define(`func', mpn_sub_n)
+ define(`func_nc', mpn_sub_nc)')
+
+MULFUNC_PROLOGUE(mpn_add_n mpn_add_nc mpn_sub_n mpn_sub_nc)
+
+ASM_START()
+PROLOGUE(func_nc)
+ SETCY( x4)
+ b L(ent)
+EPILOGUE()
+PROLOGUE(func)
+ CLRCY
+L(ent): tbz n, #0, L(b0)
+
+ ldr x4, [up],#8
+ ldr x6, [vp],#8
+ sub n, n, #1
+ ADDSUBC x8, x4, x6
+ str x8, [rp],#8
+ cbz n, L(rt)
+
+L(b0): ldp x4, x5, [up],#16
+ ldp x6, x7, [vp],#16
+ sub n, n, #2
+ cbz n, L(end)
+
+L(top): ADDSUBC x8, x4, x6
+ ADDSUBC x9, x5, x7
+ ldp x4, x5, [up]
+ add up, up, #16
+ ldp x6, x7, [vp]
+ add vp, vp, #16
+ stp x8, x9, [rp],#16
+ sub n, n, #2
+ cbnz n, L(top)
+
+L(end): ADDSUBC x8, x4, x6
+ ADDSUBC x9, x5, x7
+ stp x8, x9, [rp]
+L(rt): RETVAL
+ ret
+EPILOGUE()
diff -r 2fa752456dd9 -r ba34e2818d6b mpn/arm64/xgene1/aorsmul_1.asm
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mpn/arm64/xgene1/aorsmul_1.asm Fri Mar 25 20:33:05 2016 +0100
@@ -0,0 +1,125 @@
+dnl ARM64 mpn_addmul_1 and mpn_submul_1
+
+dnl Contributed to the GNU project by Torbjörn Granlund.
+
+dnl Copyright 2013, 2015 Free Software Foundation, Inc.
+
+dnl This file is part of the GNU MP Library.
+dnl
+dnl The GNU MP Library is free software; you can redistribute it and/or modify
+dnl it under the terms of either:
+dnl
+dnl * the GNU Lesser General Public License as published by the Free
+dnl Software Foundation; either version 3 of the License, or (at your
+dnl option) any later version.
+dnl
+dnl or
+dnl
+dnl * the GNU General Public License as published by the Free Software
+dnl Foundation; either version 2 of the License, or (at your option) any
+dnl later version.
+dnl
+dnl or both in parallel, as here.
+dnl
+dnl The GNU MP Library is distributed in the hope that it will be useful, but
+dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+dnl for more details.
+dnl
+dnl You should have received copies of the GNU General Public License and the
+dnl GNU Lesser General Public License along with the GNU MP Library. If not,
+dnl see https://www.gnu.org/licenses/.
+
+include(`../config.m4')
+
+C cycles/limb
+C Cortex-A53 ?
+C Cortex-A57 ?
+C X-Gene 5.75
+
+changecom(blah)
+
+define(`rp', `x0')
+define(`up', `x1')
+define(`n', `x2')
+define(`v0', `x3')
+
+ifdef(`OPERATION_addmul_1', `
+ define(`ADDSUB', adds)
+ define(`ADDSUBC', adcs)
+ define(`COND', `cc')
+ define(`func', mpn_addmul_1)')
+ifdef(`OPERATION_submul_1', `
+ define(`ADDSUB', subs)
+ define(`ADDSUBC', sbcs)
+ define(`COND', `cs')
+ define(`func', mpn_submul_1)')
+
+MULFUNC_PROLOGUE(mpn_addmul_1 mpn_submul_1)
+
+PROLOGUE(func)
+ mov x15, #0
+
+ tbz n, #0, L(1)
+
+ ldr x4, [up],#8
+ mul x8, x4, v0
+ umulh x12, x4, v0
+ adds x8, x8, x15
+ ldr x4, [rp,#0]
+ ADDSUB x8, x4, x8
+ csinc x15, x12, x12, COND
+ str x8, [rp],#8
+
+L(1): tbz n, #1, L(2)
+
+ ldp x4, x5, [up],#16
+ mul x8, x4, v0
+ umulh x12, x4, v0
+ mul x9, x5, v0
+ umulh x13, x5, v0
+ adds x8, x8, x15
+ adcs x9, x9, x12
+ ldp x4, x5, [rp,#0]
+ adc x15, x13, xzr
+ sub n, n, #1
+ ADDSUB x8, x4, x8
+ ADDSUBC x9, x5, x9
+ csinc x15, x15, x15, COND
+ stp x8, x9, [rp],#16
+
+L(2): lsr n, n, #2
+ cbz n, L(end)
+
+L(top): ldp x4, x5, [up]
+ ldp x6, x7, [up,#16]
+ add up, up, #32
+ mul x8, x4, v0
+ umulh x12, x4, v0
+ mul x9, x5, v0
+ umulh x13, x5, v0
+ adds x8, x8, x15
+ mul x10, x6, v0
+ umulh x14, x6, v0
+ adcs x9, x9, x12
+ mul x11, x7, v0
+ umulh x15, x7, v0
+ adcs x10, x10, x13
+ ldp x4, x5, [rp,#0]
+ adcs x11, x11, x14
+ ldp x6, x7, [rp,#16]
+ adc x15, x15, xzr
+ ADDSUB x8, x4, x8
+ ADDSUBC x9, x5, x9
+ ADDSUBC x10, x6, x10
+ ADDSUBC x11, x7, x11
+ stp x8, x9, [rp]
+ csinc x15, x15, x15, COND
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