[Gmp-commit] /var/hg/gmp: Add more CPUs, use CPU code names.
mercurial at gmplib.org
mercurial at gmplib.org
Sat Mar 14 23:19:26 UTC 2015
details: /var/hg/gmp/rev/2ac39f74cb20
changeset: 16557:2ac39f74cb20
user: Torbjorn Granlund <torbjorng at google.com>
date: Sun Mar 15 00:19:22 2015 +0100
description:
Add more CPUs, use CPU code names.
diffstat:
ChangeLog | 6 ++++++
config.guess | 57 ++++++++++++++++++++++++++++++---------------------------
config.sub | 2 +-
configure.ac | 30 +++++++++++++++++++++++++-----
4 files changed, 62 insertions(+), 33 deletions(-)
diffs (188 lines):
diff -r 2d027c920892 -r 2ac39f74cb20 ChangeLog
--- a/ChangeLog Sat Feb 21 19:59:36 2015 +0100
+++ b/ChangeLog Sun Mar 15 00:19:22 2015 +0100
@@ -1,3 +1,9 @@
+2015-03-15 <torbjorng at google.com>
+
+ * config.guess: Add more CPUs, use CPU code names.
+ * config.sub: Corresponding changes.
+ * configure.ac: Corresponding changes.
+
2015-02-21 Niels Möller <nisse at lysator.liu.se>
* gmp-h.in (mpn_divexact_1): New public declaration.
diff -r 2d027c920892 -r 2ac39f74cb20 config.guess
--- a/config.guess Sat Feb 21 19:59:36 2015 +0100
+++ b/config.guess Sun Mar 15 00:19:22 2015 +0100
@@ -807,39 +807,42 @@
else if (model <= 0x0c) modelstr = "pentium3";
else if (model <= 0x0e) modelstr = "pentiumm";
else if (model <= 0x19) cpu_64bit = 1, modelstr = "core2";
- else if (model == 0x1a) cpu_64bit = 1, modelstr = "coreinhm"; /* NHM Gainestown */
- else if (model == 0x1c) cpu_64bit = 1, modelstr = "atom"; /* Silverthorne */
- else if (model == 0x1d) cpu_64bit = 1, modelstr = "core2"; /* PNR Dunnington */
- else if (model == 0x1e) cpu_64bit = 1, modelstr = "coreinhm"; /* NHM Lynnfield/Jasper */
- else if (model == 0x25) cpu_64bit = 1, modelstr = "coreiwsm"; /* WSM Clarkdale/Arrandale */
- else if (model == 0x26) cpu_64bit = 1, modelstr = "atom"; /* Lincroft */
- else if (model == 0x27) cpu_64bit = 1, modelstr = "atom"; /* Saltwell */
- else if (model == 0x2a) cpu_64bit = 1, modelstr = "coreisbr"; /* SB */
- else if (model == 0x2c) cpu_64bit = 1, modelstr = "coreiwsm"; /* WSM Gulftown */
- else if (model == 0x2d) cpu_64bit = 1, modelstr = "coreisbr"; /* SBC-EP */
- else if (model == 0x2e) cpu_64bit = 1, modelstr = "coreinhm"; /* NHM Beckton */
- else if (model == 0x2f) cpu_64bit = 1, modelstr = "coreiwsm"; /* WSM Eagleton */
- else if (model == 0x36) cpu_64bit = 1, modelstr = "atom"; /* Cedarview/Saltwell */
- else if (model == 0x37) cpu_64bit = 1, modelstr = "coreinhm"; /* Atom Silvermont */
- else if (model == 0x3a) cpu_64bit = 1, modelstr = "coreisbr"; /* IBR */
- else if (model == 0x3c) cpu_64bit = 1, modelstr = "coreihwl"; /* Haswell client */
- else if (model == 0x3d) cpu_64bit = 1, modelstr = "coreibwl"; /* Broadwell */
- else if (model == 0x3e) cpu_64bit = 1, modelstr = "coreisbr"; /* Ivytown */
- else if (model == 0x3f) cpu_64bit = 1, modelstr = "coreihwl"; /* Haswell server */
- else if (model == 0x45) cpu_64bit = 1, modelstr = "coreihwl"; /* Haswell ULT */
- else if (model == 0x46) cpu_64bit = 1, modelstr = "coreihwl"; /* Crystal Well */
- else if (model == 0x4d) cpu_64bit = 1, modelstr = "coreinhm"; /* Silvermont/Avoton */
- else if (model == 0x4f) cpu_64bit = 1, modelstr = "coreibwl"; /* Broadwell server */
- else if (model == 0x56) cpu_64bit = 1, modelstr = "coreibwl"; /* Broadwell microserver */
- else cpu_64bit = 1, modelstr = "corei"; /* default */
+ else if (model == 0x1a) cpu_64bit = 1, modelstr = "nehalem"; /* NHM Gainestown */
+ else if (model == 0x1c) cpu_64bit = 1, modelstr = "atom"; /* Silverthorne */
+ else if (model == 0x1d) cpu_64bit = 1, modelstr = "core2"; /* PNR Dunnington */
+ else if (model == 0x1e) cpu_64bit = 1, modelstr = "nehalem"; /* NHM Lynnfield/Jasper */
+ else if (model == 0x25) cpu_64bit = 1, modelstr = "westmere"; /* WSM Clarkdale/Arrandale */
+ else if (model == 0x26) cpu_64bit = 1, modelstr = "atom"; /* Lincroft */
+ else if (model == 0x27) cpu_64bit = 1, modelstr = "atom"; /* Saltwell */
+ else if (model == 0x2a) cpu_64bit = 1, modelstr = "sandybridge";/* SB */
+ else if (model == 0x2c) cpu_64bit = 1, modelstr = "westmere"; /* WSM Gulftown */
+ else if (model == 0x2d) cpu_64bit = 1, modelstr = "sandybridge";/* SBC-EP */
+ else if (model == 0x2e) cpu_64bit = 1, modelstr = "nehalem"; /* NHM Beckton */
+ else if (model == 0x2f) cpu_64bit = 1, modelstr = "westmere"; /* WSM Eagleton */
+ else if (model == 0x36) cpu_64bit = 1, modelstr = "atom"; /* Cedarview/Saltwell */
+ else if (model == 0x37) cpu_64bit = 1, modelstr = "silvermont"; /* Atom Silvermont */
+ else if (model == 0x3a) cpu_64bit = 1, modelstr = "ivybridge"; /* IBR */
+ else if (model == 0x3c) cpu_64bit = 1, modelstr = "haswell"; /* Haswell client */
+ else if (model == 0x3d) cpu_64bit = 1, modelstr = "broadwell"; /* Broadwell */
+ else if (model == 0x3e) cpu_64bit = 1, modelstr = "ivybridge"; /* Ivytown */
+ else if (model == 0x3f) cpu_64bit = 1, modelstr = "haswell"; /* Haswell server */
+ else if (model == 0x45) cpu_64bit = 1, modelstr = "haswell"; /* Haswell ULT */
+ else if (model == 0x46) cpu_64bit = 1, modelstr = "haswell"; /* Crystal Well */
+ else if (model == 0x47) cpu_64bit = 1, modelstr = "broadwell"; /* Broadwell */
+ else if (model == 0x4a) cpu_64bit = 1, modelstr = "silvermont"; /* Silvermont */
+ else if (model == 0x4c) cpu_64bit = 1, modelstr = "silvermont"; /* Airmont */
+ else if (model == 0x4d) cpu_64bit = 1, modelstr = "silvermont"; /* Silvermont/Avoton */
+ else if (model == 0x4f) cpu_64bit = 1, modelstr = "broadwell"; /* Broadwell server */
+ else if (model == 0x56) cpu_64bit = 1, modelstr = "broadwell"; /* Broadwell microserver */
+ else cpu_64bit = 1, modelstr = "nehalem"; /* default */
- if (strcmp (modelstr, "coreihwl") == 0)
+ if (strcmp (modelstr, "haswell") == 0)
{
/* Some Haswells lack BMI2. Let them appear as Sandybridges for
now. */
CPUID (dummy_string, 7);
if ((dummy_string[0 + 8 / 8] & (1 << (8 % 8))) == 0)
- modelstr = "coreisbr";
+ modelstr = "sandybridge";
}
break;
diff -r 2d027c920892 -r 2ac39f74cb20 config.sub
--- a/config.sub Sat Feb 21 19:59:36 2015 +0100
+++ b/config.sub Sun Mar 15 00:19:22 2015 +0100
@@ -102,7 +102,7 @@
test_cpu=ia64 ;;
pentium | pentiummmx | pentiumpro | pentium[234m] | k[567] | k6[23] | geode | athlon | viac3*)
test_cpu=i386 ;;
-athlon64 | atom | core2 | corei* | opteron | k[89] | k10 | bobcat | jaguar* | bulldozer* | piledriver* | steamroller* | excavator* | nano)
+athlon64 | atom | silvermont | core2 | corei* | opteron | k[89] | k10 | bobcat | jaguar* | bulldozer* | piledriver* | steamroller* | excavator* | nano | nehalem* | westmere* | sandybridge | ivybridge | haswell | broadwell)
test_cpu=x86_64 ;;
power[2-9] | power2sc)
test_cpu=power ;;
diff -r 2d027c920892 -r 2ac39f74cb20 configure.ac
--- a/configure.ac Sat Feb 21 19:59:36 2015 +0100
+++ b/configure.ac Sun Mar 15 00:19:22 2015 +0100
@@ -658,6 +658,17 @@
path="arm/v6t2 arm/v6 arm/v5 arm"
gcc_cflags_arch="-march=armv7-a"
;;
+ armcortexa7)
+ path="arm/v6t2 arm/v6 arm/v5 arm"
+ gcc_cflags_arch="-march=armv7-a"
+ gcc_cflags_tune="-mtune=cortex-a7"
+ ;;
+ armcortexa7neon)
+ path="arm/neon arm/v6t2 arm/v6 arm/v5 arm"
+ gcc_cflags_arch="-march=armv7-a"
+ gcc_cflags_neon="-mfpu=neon"
+ gcc_cflags_tune="-mtune=cortex-a7"
+ ;;
armcortexa8)
path="arm/v6t2 arm/v6 arm/v5 arm"
gcc_cflags_arch="-march=armv7-a"
@@ -837,6 +848,7 @@
# But icc miscompiles GMP at any optimization level, at higher levels
# it miscompiles more files...
icc_cflags_opt="-O2 -O1"
+ icc_cflags_opt_maybe="-fp-model~precise"
;;
*-*-hpux*)
@@ -1574,6 +1586,7 @@
icc_cflags="-no-gcc"
icc_cflags_optlist="opt"
icc_cflags_opt="-O3 -O2 -O1"
+ icc_cflags_opt_maybe="-fp-model~precise"
any_32_testlist="sizeof-long-4"
gcc_cflags_optlist="cpu arch noavx"
CALLING_CONVENTIONS_OBJS='x86call.lo x86check$U.lo'
@@ -1762,25 +1775,26 @@
path="x86/core2 x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
path_64="x86_64/core2 x86_64"
;;
- corei | coreinhm | coreiwsm)
+ corei | coreinhm | coreiwsm | nehalem | westmere)
gcc_cflags_cpu="-mtune=corei7 -mtune=core2 -mtune=k8"
gcc_cflags_arch="-march=corei7 -march=core2 -march=core2~-mno-sse2 -march=k8 -march=k8~-mno-sse2"
path="x86/coreinhm x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
path_64="x86_64/coreinhm x86_64/core2 x86_64"
;;
- coreisbr | coreisbrnoavx)
+ coreisbr | coreisbrnoavx | coreiibr | coreiibrnoavx | \
+ sandybridge | sandybridgenoavx | ivybridge | ivybridgenoavx)
gcc_cflags_cpu="-mtune=corei7 -mtune=core2 -mtune=k8"
gcc_cflags_arch="-march=corei7 -march=core2 -march=core2~-mno-sse2 -march=k8 -march=k8~-mno-sse2"
path="x86/coreisbr x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
path_64="x86_64/coreisbr x86_64/coreinhm x86_64/core2 x86_64"
;;
- coreihwl | coreihwlnoavx)
+ coreihwl | coreihwlnoavx | haswell | haswellnoavx)
gcc_cflags_cpu="-mtune=corei7 -mtune=core2 -mtune=k8"
gcc_cflags_arch="-march=corei7 -march=core2 -march=core2~-mno-sse2 -march=k8 -march=k8~-mno-sse2"
path="x86/coreisbr x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
path_64="x86_64/coreihwl x86_64/coreisbr x86_64/coreinhm x86_64/core2 x86_64"
;;
- coreibwl | coreibwlnoavx)
+ coreibwl | coreibwlnoavx | broadwell | broadwellnoavx)
gcc_cflags_cpu="-mtune=corei7 -mtune=core2 -mtune=k8"
gcc_cflags_arch="-march=corei7 -march=core2 -march=core2~-mno-sse2 -march=k8 -march=k8~-mno-sse2"
path="x86/coreisbr x86/p6/sse2 x86/p6/p3mmx x86/p6/mmx x86/p6 x86/mmx x86"
@@ -1793,6 +1807,12 @@
path="x86/atom/sse2 x86/atom/mmx x86/atom x86/mmx x86"
path_64="x86_64/atom x86_64"
;;
+ silvermont)
+ gcc_cflags_cpu="-mtune=slm -mtune=atom -mtune=pentium3"
+ gcc_cflags_arch="-march=slm -march=atom -march=pentium3"
+ path="x86/atom/sse2 x86/atom/mmx x86/atom x86/mmx x86"
+ path_64="x86_64/silvermont x86_64/atom x86_64"
+ ;;
nano)
gcc_cflags_cpu="-mtune=nano"
gcc_cflags_arch="-march=nano"
@@ -2137,7 +2157,7 @@
fat_path="x86_64 x86_64/fat
x86_64/k8 x86_64/k10 x86_64/bd1 x86_64/bobcat
x86_64/pentium4 x86_64/core2 x86_64/coreinhm x86_64/coreisbr
- x86_64/coreihwl x86_64/atom x86_64/nano"
+ x86_64/coreihwl x86_64/atom x86_64/silvermont x86_64/nano"
fat_functions="$fat_functions addmul_2 addlsh1_n addlsh2_n sublsh1_n"
fi
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