[Gmp-commit] /var/hg/gmp: Update fat support.

[mercurial at gmplib.org]

details:   /var/hg/gmp/rev/0fe018bd50ee
changeset: 16776:0fe018bd50ee
user:      Torbjorn Granlund <torbjorng at google.com>
date:      Sun Aug 23 21:30:13 2015 +0200
description:
Update fat support.

diffstat:

 ChangeLog            |   7 +++++++
 configure.ac         |   6 +++---
 mpn/x86_64/fat/fat.c |  20 +++++++++++++++-----
 3 files changed, 25 insertions(+), 8 deletions(-)

diffs (77 lines):

diff -r 1fac4f92ac04 -r 0fe018bd50ee ChangeLog
--- a/ChangeLog	Thu Aug 20 08:19:02 2015 +0200
+++ b/ChangeLog	Sun Aug 23 21:30:13 2015 +0200
@@ -1,3 +1,10 @@
+2015-08-23  Torbjörn Granlund  <torbjorng at google.com>
+
+	* mpn/x86_64/fat/fat.c (__gmpn_cpuvec_init): Add more entries, handle
+	Broadwell separately.
+
+	* configure.ac (fat_path): Add coreibwl.
+
 2015-08-18 Marco Bodrato <bodrato at mail.dm.unipi.it>
 
 	* mpn/generic/rootrem.c (logbased_root): New function.
diff -r 1fac4f92ac04 -r 0fe018bd50ee configure.ac
--- a/configure.ac	Thu Aug 20 08:19:02 2015 +0200
+++ b/configure.ac	Sun Aug 23 21:30:13 2015 +0200
@@ -2161,9 +2161,9 @@
 	extra_functions_64="$extra_functions_64 fat fat_entry"
 	path_64="x86_64/fat x86_64"
 	fat_path="x86_64 x86_64/fat
-		  x86_64/k8 x86_64/k10 x86_64/bd1 x86_64/bobcat
-		  x86_64/pentium4 x86_64/core2 x86_64/coreinhm x86_64/coreisbr
-		  x86_64/coreihwl x86_64/atom x86_64/silvermont x86_64/nano"
+		  x86_64/k8 x86_64/k10 x86_64/bd1 x86_64/bobcat x86_64/pentium4
+		  x86_64/core2 x86_64/coreinhm x86_64/coreisbr x86_64/coreihwl
+		  x86_64/coreibwl x86_64/atom x86_64/silvermont x86_64/nano"
 	fat_functions="$fat_functions addmul_2 addlsh1_n addlsh2_n sublsh1_n"
       fi
 
diff -r 1fac4f92ac04 -r 0fe018bd50ee mpn/x86_64/fat/fat.c
--- a/mpn/x86_64/fat/fat.c	Thu Aug 20 08:19:02 2015 +0200
+++ b/mpn/x86_64/fat/fat.c	Sun Aug 23 21:30:13 2015 +0200
@@ -272,8 +272,10 @@
 	    case 0x2c:		/* WSM Gulftown */
 	    case 0x2e:		/* NHM Beckton */
 	    case 0x2f:		/* WSM Eagleton */
-	    case 0x37:		/* Atom Silvermont */
-	    case 0x4d:		/* Atom Silvermont/Avoton */
+	    case 0x37:		/* Silvermont */
+	    case 0x4a:		/* Silvermont */
+	    case 0x4c:		/* Airmont */
+	    case 0x4d:		/* Silvermont/Avoton */
 	      CPUVEC_SETUP_core2;
 	      CPUVEC_SETUP_coreinhm;
 	      break;
@@ -287,12 +289,9 @@
 	      CPUVEC_SETUP_coreisbr;
 	      break;
 	    case 0x3c:		/* Haswell client */
-	    case 0x3d:		/* Broadwell */
 	    case 0x3f:		/* Haswell server */
 	    case 0x45:		/* Haswell ULT */
 	    case 0x46:		/* Crystal Well */
-	    case 0x4f:		/* Broadwell server */
-	    case 0x56:		/* Broadwell microserver */
 	      CPUVEC_SETUP_core2;
 	      CPUVEC_SETUP_coreinhm;
 	      CPUVEC_SETUP_coreisbr;
@@ -302,6 +301,17 @@
 	      if ((dummy_string[0 + 8 / 8] & (1 << (8 % 8))) != 0)
 		CPUVEC_SETUP_coreihwl;
 	      break;
+	    case 0x3d:		/* Broadwell */
+	    case 0x47:		/* Broadwell */
+	    case 0x4f:		/* Broadwell server */
+	    case 0x56:		/* Broadwell microserver */
+	    case 0x5e:		/* Skylake */
+	      CPUVEC_SETUP_core2;
+	      CPUVEC_SETUP_coreinhm;
+	      CPUVEC_SETUP_coreisbr;
+	      CPUVEC_SETUP_coreihwl;
+	      CPUVEC_SETUP_coreibwl;
+	      break;
 	    }
 	  break;