[Gmp-commit] /var/hg/gmp: Use official b.cond syntax on aarch64.

[mercurial at gmplib.org]

details:   /var/hg/gmp/rev/b5c435fb5e22
changeset: 16369:b5c435fb5e22
user:      Marc Glisse <marc.glisse at inria.fr>
date:      Thu Apr 03 22:36:27 2014 +0200
description:
Use official b.cond syntax on aarch64.

diffstat:

 ChangeLog           |   4 ++++
 mpn/arm64/gcd_1.asm |  10 +++++-----
 mpn/arm64/mul_1.asm |   4 ++--
 3 files changed, 11 insertions(+), 7 deletions(-)

diffs (69 lines):

diff -r 267de6866b9a -r b5c435fb5e22 ChangeLog
--- a/ChangeLog	Thu Apr 03 16:32:29 2014 +0200
+++ b/ChangeLog	Thu Apr 03 22:36:27 2014 +0200
@@ -1,3 +1,7 @@
+2014-04-03  Marc Glisse  <marc.glisse at inria.fr>
+
+	* mpn/arm64/mul_1.asm, mpn/arm64/gcd_1.asm: Use official b.cond syntax.
+
 2014-04-03  Torbjorn Granlund  <tege at gmplib.org>
 
 	* config.guess: Append "noavx" for CPUs which have AVX but where the
diff -r 267de6866b9a -r b5c435fb5e22 mpn/arm64/gcd_1.asm
--- a/mpn/arm64/gcd_1.asm	Thu Apr 03 16:32:29 2014 +0200
+++ b/mpn/arm64/gcd_1.asm	Thu Apr 03 22:36:27 2014 +0200
@@ -74,19 +74,19 @@
 	mov	x19, v0
 
 	cmp	n, #1
-	bne	L(nby1)
+	b.ne	L(nby1)
 
 C Both U and V are single limbs, reduce with bmod if u0 >> v0.
 	ldr	x3, [up]
 	cmp	v0, x3, lsr #BMOD_THRES_LOG2
-	bhi	L(red1)
+	b.hi	L(red1)
 
 L(bmod):mov	x3, #0			C carry argument
 	bl	mpn_modexact_1c_odd
 	b	L(red0)
 
 L(nby1):cmp	n, #BMOD_1_TO_MOD_1_THRESHOLD
-	blo	L(bmod)
+	b.lo	L(bmod)
 
 	bl	mpn_mod_1
 
@@ -94,7 +94,7 @@
 L(red1):cmp	x3, #0
 	rbit	x12, x3
 	clz	x12, x12
-	bne	L(mid)
+	b.ne	L(mid)
 	b	L(end)
 
 	ALIGN(8)
@@ -116,7 +116,7 @@
 ')
 	rbit	x12, x1
 	clz	x12, x12		C
-	bne	L(top)			C
+	b.ne	L(top)			C
 
 L(end):	lsl	x0, x19, x20
 	ldp     x19, x20, [sp,#16]
diff -r 267de6866b9a -r b5c435fb5e22 mpn/arm64/mul_1.asm
--- a/mpn/arm64/mul_1.asm	Thu Apr 03 16:32:29 2014 +0200
+++ b/mpn/arm64/mul_1.asm	Thu Apr 03 22:36:27 2014 +0200
@@ -48,8 +48,8 @@
 	and	n, n, #-4
 	cbz	x6, L(fi0)
 	cmp	x6, #2
-	bcc	L(fi1)
-	beq	L(fi2)
+	b.cc	L(fi1)
+	b.eq	L(fi2)
 
 L(fi3):	mul	x8, x12, v0
 	umulh	x13, x12, v0