[Gmp-commit] /var/hg/gmp: 3 new changesets
mercurial at gmplib.org
mercurial at gmplib.org
Sat May 4 11:48:29 CEST 2013
details: /var/hg/gmp/rev/b564b87d1638
changeset: 15793:b564b87d1638
user: David S. Miller
date: Sat May 04 11:45:28 2013 +0200
description:
Add T4 and T3 timings.
details: /var/hg/gmp/rev/f4e795299c0b
changeset: 15794:f4e795299c0b
user: David S. Miller
date: Sat May 04 11:48:08 2013 +0200
description:
Make tune/speed work when addlsh1_n etc are macros.
details: /var/hg/gmp/rev/2fa64d420f81
changeset: 15795:2fa64d420f81
user: Torbjorn Granlund <tege at gmplib.org>
date: Sat May 04 11:48:25 2013 +0200
description:
ChangeLog
diffstat:
ChangeLog | 13 +++++++++++++
mpn/sparc64/ultrasparct3/addmul_1.asm | 4 ++--
mpn/sparc64/ultrasparct3/aormul_4.asm | 4 ++--
mpn/sparc64/ultrasparct3/aorslsh_n.asm | 4 ++--
mpn/sparc64/ultrasparct3/cnd_aors_n.asm | 4 ++--
mpn/sparc64/ultrasparct3/dive_1.asm | 2 +-
mpn/sparc64/ultrasparct3/submul_1.asm | 4 ++--
tune/common.c | 12 ++++++------
tune/speed.c | 12 ++++++------
9 files changed, 36 insertions(+), 23 deletions(-)
diffs (198 lines):
diff -r 7b28672f34d6 -r 2fa64d420f81 ChangeLog
--- a/ChangeLog Fri May 03 11:49:59 2013 +0200
+++ b/ChangeLog Sat May 04 11:48:25 2013 +0200
@@ -1,3 +1,16 @@
+2013-05-03 David S. Miller <davem at davemloft.net>
+
+ * tune/common.c (speed_mpn_addlsh1_n, speed_mpn_sublsh1_n,
+ speed_mpn_rsblsh1_n, speed_mpn_addlsh2_n, speed_mpn_sublsh2_n,
+ speed_mpn_rsblsh2_n): Don't define if these routines are macros.
+ * tune/speed.c (routine): Likewise don't table if they are macros.
+
+ * mpn/sparc64/ultrasparct3/addmul_1.asm: Add T4 and T3 timings.
+ * mpn/sparc64/ultrasparct3/aormul_4.asm: Likewise.
+ * mpn/sparc64/ultrasparct3/aorslsh_n.asm: Likewise.
+ * mpn/sparc64/ultrasparct3/cnd_aors_n.asm: Likewise.
+ * mpn/sparc64/ultrasparct3/submul_1.asm: Likewise.
+
2013-05-03 Torbjorn Granlund <tege at gmplib.org>
* mpn/sparc64/ultrasparct3/aorslsh_n.asm: Invoke INITCY where it has
diff -r 7b28672f34d6 -r 2fa64d420f81 mpn/sparc64/ultrasparct3/addmul_1.asm
--- a/mpn/sparc64/ultrasparct3/addmul_1.asm Fri May 03 11:49:59 2013 +0200
+++ b/mpn/sparc64/ultrasparct3/addmul_1.asm Sat May 04 11:48:25 2013 +0200
@@ -22,8 +22,8 @@
include(`../config.m4')
C cycles/limb
-C UltraSPARC T3: ?
-C UltraSPARC T4: 4.25 hopefully
+C UltraSPARC T3: 26
+C UltraSPARC T4: 4.5
C INPUT PARAMETERS
define(`rp', `%i0')
diff -r 7b28672f34d6 -r 2fa64d420f81 mpn/sparc64/ultrasparct3/aormul_4.asm
--- a/mpn/sparc64/ultrasparct3/aormul_4.asm Fri May 03 11:49:59 2013 +0200
+++ b/mpn/sparc64/ultrasparct3/aormul_4.asm Sat May 04 11:48:25 2013 +0200
@@ -24,8 +24,8 @@
C cycles/limb cycles/limb
C mul_4 addmul_4
-C UltraSPARC T3: ? ?
-C UltraSPARC T4: 2.5? 2.75?
+C UltraSPARC T3: 21.5 22.0
+C UltraSPARC T4: 2.625 2.75
C The code is well-scheduled and relies on OoO very little. There is hope that
diff -r 7b28672f34d6 -r 2fa64d420f81 mpn/sparc64/ultrasparct3/aorslsh_n.asm
--- a/mpn/sparc64/ultrasparct3/aorslsh_n.asm Fri May 03 11:49:59 2013 +0200
+++ b/mpn/sparc64/ultrasparct3/aorslsh_n.asm Sat May 04 11:48:25 2013 +0200
@@ -22,8 +22,8 @@
include(`../config.m4')
C cycles/limb
-C UltraSPARC T3: ?
-C UltraSPARC T4: 4 c/l hopefully
+C UltraSPARC T3: 11
+C UltraSPARC T4: 4
C For sublsh_n we combine the two shifted limbs using xnor, using the identity
C (a xor not b) = (not (a xor b)) which equals (not (a or b)) when (a and b) =
diff -r 7b28672f34d6 -r 2fa64d420f81 mpn/sparc64/ultrasparct3/cnd_aors_n.asm
--- a/mpn/sparc64/ultrasparct3/cnd_aors_n.asm Fri May 03 11:49:59 2013 +0200
+++ b/mpn/sparc64/ultrasparct3/cnd_aors_n.asm Sat May 04 11:48:25 2013 +0200
@@ -22,8 +22,8 @@
include(`../config.m4')
C cycles/limb
-C UltraSPARC T3: ?
-C UltraSPARC T4: 3 hopefully
+C UltraSPARC T3: 8.5
+C UltraSPARC T4: 3
C We use a double-pointer trick to allow indexed addressing. Its setup
C cost might be a problem in these functions, since we don't expect huge n
diff -r 7b28672f34d6 -r 2fa64d420f81 mpn/sparc64/ultrasparct3/dive_1.asm
--- a/mpn/sparc64/ultrasparct3/dive_1.asm Fri May 03 11:49:59 2013 +0200
+++ b/mpn/sparc64/ultrasparct3/dive_1.asm Sat May 04 11:48:25 2013 +0200
@@ -22,7 +22,7 @@
include(`../config.m4')
C cycles/limb
-C UltraSPARC T3: ?
+C UltraSPARC T3: 31
C UltraSPARC T4/T5: 20-26 hits 20 early, then sharply drops
C INPUT PARAMETERS
diff -r 7b28672f34d6 -r 2fa64d420f81 mpn/sparc64/ultrasparct3/submul_1.asm
--- a/mpn/sparc64/ultrasparct3/submul_1.asm Fri May 03 11:49:59 2013 +0200
+++ b/mpn/sparc64/ultrasparct3/submul_1.asm Sat May 04 11:48:25 2013 +0200
@@ -22,8 +22,8 @@
include(`../config.m4')
C cycles/limb
-C UltraSPARC T3: ?
-C UltraSPARC T4: 4.5 hopefully
+C UltraSPARC T3: 26
+C UltraSPARC T4: 4.5
C INPUT PARAMETERS
define(`rp', `%i0')
diff -r 7b28672f34d6 -r 2fa64d420f81 tune/common.c
--- a/tune/common.c Fri May 03 11:49:59 2013 +0200
+++ b/tune/common.c Sat May 04 11:48:25 2013 +0200
@@ -989,14 +989,14 @@
}
#endif
-#if HAVE_NATIVE_mpn_addlsh1_n
+#if HAVE_NATIVE_mpn_addlsh1_n == 1
double
speed_mpn_addlsh1_n (struct speed_params *s)
{
SPEED_ROUTINE_MPN_BINARY_N (mpn_addlsh1_n);
}
#endif
-#if HAVE_NATIVE_mpn_sublsh1_n
+#if HAVE_NATIVE_mpn_sublsh1_n == 1
double
speed_mpn_sublsh1_n (struct speed_params *s)
{
@@ -1024,21 +1024,21 @@
SPEED_ROUTINE_MPN_COPY (mpn_sublsh1_n_ip1);
}
#endif
-#if HAVE_NATIVE_mpn_rsblsh1_n
+#if HAVE_NATIVE_mpn_rsblsh1_n == 1
double
speed_mpn_rsblsh1_n (struct speed_params *s)
{
SPEED_ROUTINE_MPN_BINARY_N (mpn_rsblsh1_n);
}
#endif
-#if HAVE_NATIVE_mpn_addlsh2_n
+#if HAVE_NATIVE_mpn_addlsh2_n == 1
double
speed_mpn_addlsh2_n (struct speed_params *s)
{
SPEED_ROUTINE_MPN_BINARY_N (mpn_addlsh2_n);
}
#endif
-#if HAVE_NATIVE_mpn_sublsh2_n
+#if HAVE_NATIVE_mpn_sublsh2_n == 1
double
speed_mpn_sublsh2_n (struct speed_params *s)
{
@@ -1066,7 +1066,7 @@
SPEED_ROUTINE_MPN_COPY (mpn_sublsh2_n_ip1);
}
#endif
-#if HAVE_NATIVE_mpn_rsblsh2_n
+#if HAVE_NATIVE_mpn_rsblsh2_n == 1
double
speed_mpn_rsblsh2_n (struct speed_params *s)
{
diff -r 7b28672f34d6 -r 2fa64d420f81 tune/speed.c
--- a/tune/speed.c Fri May 03 11:49:59 2013 +0200
+++ b/tune/speed.c Sat May 04 11:48:25 2013 +0200
@@ -413,10 +413,10 @@
{ "mpn_copyd", speed_mpn_copyd },
#endif
{ "mpn_tabselect", speed_mpn_tabselect, FLAG_R_OPTIONAL },
-#if HAVE_NATIVE_mpn_addlsh1_n
+#if HAVE_NATIVE_mpn_addlsh1_n == 1
{ "mpn_addlsh1_n", speed_mpn_addlsh1_n, FLAG_R_OPTIONAL },
#endif
-#if HAVE_NATIVE_mpn_sublsh1_n
+#if HAVE_NATIVE_mpn_sublsh1_n == 1
{ "mpn_sublsh1_n", speed_mpn_sublsh1_n, FLAG_R_OPTIONAL },
#endif
#if HAVE_NATIVE_mpn_addlsh1_n_ip1
@@ -428,13 +428,13 @@
#if HAVE_NATIVE_mpn_sublsh1_n_ip1
{ "mpn_sublsh1_n_ip1", speed_mpn_sublsh1_n_ip1 },
#endif
-#if HAVE_NATIVE_mpn_rsblsh1_n
+#if HAVE_NATIVE_mpn_rsblsh1_n == 1
{ "mpn_rsblsh1_n", speed_mpn_rsblsh1_n, FLAG_R_OPTIONAL },
#endif
-#if HAVE_NATIVE_mpn_addlsh2_n
+#if HAVE_NATIVE_mpn_addlsh2_n == 1
{ "mpn_addlsh2_n", speed_mpn_addlsh2_n, FLAG_R_OPTIONAL },
#endif
-#if HAVE_NATIVE_mpn_sublsh2_n
+#if HAVE_NATIVE_mpn_sublsh2_n == 1
{ "mpn_sublsh2_n", speed_mpn_sublsh2_n, FLAG_R_OPTIONAL },
#endif
#if HAVE_NATIVE_mpn_addlsh2_n_ip1
@@ -446,7 +446,7 @@
#if HAVE_NATIVE_mpn_sublsh2_n_ip1
{ "mpn_sublsh2_n_ip1", speed_mpn_sublsh2_n_ip1 },
#endif
-#if HAVE_NATIVE_mpn_rsblsh2_n
+#if HAVE_NATIVE_mpn_rsblsh2_n == 1
{ "mpn_rsblsh2_n", speed_mpn_rsblsh2_n, FLAG_R_OPTIONAL },
#endif
#if HAVE_NATIVE_mpn_addlsh_n
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