[Gmp-commit] /var/hg/gmp: 4 new changesets
mercurial at gmplib.org
mercurial at gmplib.org
Sat Aug 31 22:27:59 CEST 2013
details: /var/hg/gmp/rev/27d6a6c79e9c
changeset: 15960:27d6a6c79e9c
user: Torbjorn Granlund <tege at gmplib.org>
date: Sat Aug 31 21:32:30 2013 +0200
description:
Fix comment typo.
details: /var/hg/gmp/rev/c3d02c8e00b5
changeset: 15961:c3d02c8e00b5
user: Torbjorn Granlund <tege at gmplib.org>
date: Sat Aug 31 21:37:10 2013 +0200
description:
Provide SBR/IBR sqr_basecase.
details: /var/hg/gmp/rev/d5812ca3e584
changeset: 15962:d5812ca3e584
user: Torbjorn Granlund <tege at gmplib.org>
date: Sat Aug 31 21:37:40 2013 +0200
description:
ChangeLog
details: /var/hg/gmp/rev/1e5460ea0f63
changeset: 15963:1e5460ea0f63
user: Torbjorn Granlund <tege at gmplib.org>
date: Sat Aug 31 22:03:50 2013 +0200
description:
Tweak for slightly better speed for relevant CPUs.
diffstat:
ChangeLog | 13 +
mpn/x86_64/bd1/mul_basecase.asm | 2 +-
mpn/x86_64/coreihwl/mul_basecase.asm | 2 +-
mpn/x86_64/coreisbr/addmul_2.asm | 2 +-
mpn/x86_64/coreisbr/mul_2.asm | 2 +-
mpn/x86_64/coreisbr/mul_basecase.asm | 2 +-
mpn/x86_64/coreisbr/sqr_basecase.asm | 473 +++++++++++++++++++++++++++++++++++
mpn/x86_64/sqr_diag_addlsh1.asm | 18 +-
8 files changed, 500 insertions(+), 14 deletions(-)
diffs (truncated from 600 to 300 lines):
diff -r a560ed2fc6af -r 1e5460ea0f63 ChangeLog
--- a/ChangeLog Sat Aug 31 18:46:59 2013 +0200
+++ b/ChangeLog Sat Aug 31 22:03:50 2013 +0200
@@ -1,3 +1,16 @@
+2013-08-31 Torbjorn Granlund <tege at gmplib.org>
+
+ * mpn/x86_64/coreisbr/sqr_basecase.asm: New file.
+
+ * mpn/x86_64/sqr_diag_addlsh1.asm: New file.
+
+2013-08-30 Torbjorn Granlund <tege at gmplib.org>
+
+ * mpn/x86_64/fat/mul_basecase.c: New file.
+ * mpn/x86_64/fat/sqr_basecase.c: New file.
+ * mpn/x86_64/fat/mullo_basecase.c: New file.
+ * mpn/x86_64/fat/redc_1.c: New file.
+
2013-08-29 Torbjorn Granlund <tege at gmplib.org>
* mpn/x86_64/k8/mul_basecase.asm: Move top-level basecase file to k8
diff -r a560ed2fc6af -r 1e5460ea0f63 mpn/x86_64/bd1/mul_basecase.asm
--- a/mpn/x86_64/bd1/mul_basecase.asm Sat Aug 31 18:46:59 2013 +0200
+++ b/mpn/x86_64/bd1/mul_basecase.asm Sat Aug 31 22:03:50 2013 +0200
@@ -50,7 +50,7 @@
C * Further micro-optimise.
C When playing with pointers, set this to $2 to fall back to conservative
-C indexing in wind-dowm code.
+C indexing in wind-down code.
define(`I',`$1')
diff -r a560ed2fc6af -r 1e5460ea0f63 mpn/x86_64/coreihwl/mul_basecase.asm
--- a/mpn/x86_64/coreihwl/mul_basecase.asm Sat Aug 31 18:46:59 2013 +0200
+++ b/mpn/x86_64/coreihwl/mul_basecase.asm Sat Aug 31 22:03:50 2013 +0200
@@ -51,7 +51,7 @@
C * Further micro-optimise.
C When playing with pointers, set this to $2 to fall back to conservative
-C indexing in wind-dowm code.
+C indexing in wind-down code.
define(`I',`$1')
diff -r a560ed2fc6af -r 1e5460ea0f63 mpn/x86_64/coreisbr/addmul_2.asm
--- a/mpn/x86_64/coreisbr/addmul_2.asm Sat Aug 31 18:46:59 2013 +0200
+++ b/mpn/x86_64/coreisbr/addmul_2.asm Sat Aug 31 22:03:50 2013 +0200
@@ -43,7 +43,7 @@
C suite written by David Harvey and Torbjorn Granlund.
C When playing with pointers, set this to $2 to fall back to conservative
-C indexing in wind-dowm code.
+C indexing in wind-down code.
define(`I',`$1')
diff -r a560ed2fc6af -r 1e5460ea0f63 mpn/x86_64/coreisbr/mul_2.asm
--- a/mpn/x86_64/coreisbr/mul_2.asm Sat Aug 31 18:46:59 2013 +0200
+++ b/mpn/x86_64/coreisbr/mul_2.asm Sat Aug 31 22:03:50 2013 +0200
@@ -43,7 +43,7 @@
C suite written by David Harvey and Torbjorn Granlund.
C When playing with pointers, set this to $2 to fall back to conservative
-C indexing in wind-dowm code.
+C indexing in wind-down code.
define(`I',`$1')
define(`rp', `%rdi') C rcx
diff -r a560ed2fc6af -r 1e5460ea0f63 mpn/x86_64/coreisbr/mul_basecase.asm
--- a/mpn/x86_64/coreisbr/mul_basecase.asm Sat Aug 31 18:46:59 2013 +0200
+++ b/mpn/x86_64/coreisbr/mul_basecase.asm Sat Aug 31 22:03:50 2013 +0200
@@ -52,7 +52,7 @@
C * Further micro-optimise.
C When playing with pointers, set this to $2 to fall back to conservative
-C indexing in wind-dowm code.
+C indexing in wind-down code.
define(`I',`$1')
diff -r a560ed2fc6af -r 1e5460ea0f63 mpn/x86_64/coreisbr/sqr_basecase.asm
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mpn/x86_64/coreisbr/sqr_basecase.asm Sat Aug 31 22:03:50 2013 +0200
@@ -0,0 +1,473 @@
+dnl AMD64 mpn_sqr_basecase optimised for Intel Sandy bridge and Ivy bridge.
+
+dnl Contributed to the GNU project by Torbjörn Granlund.
+
+dnl Copyright 2008, 2009, 2011, 2012, 2013 Free Software Foundation, Inc.
+
+dnl This file is part of the GNU MP Library.
+
+dnl The GNU MP Library is free software; you can redistribute it and/or modify
+dnl it under the terms of the GNU Lesser General Public License as published
+dnl by the Free Software Foundation; either version 3 of the License, or (at
+dnl your option) any later version.
+
+dnl The GNU MP Library is distributed in the hope that it will be useful, but
+dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+dnl License for more details.
+
+dnl You should have received a copy of the GNU Lesser General Public License
+dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/.
+
+include(`../config.m4')
+
+C cycles/limb mul_2 addmul_2 sqr_diag_addlsh1
+C AMD K8,K9 ? ? ?
+C AMD K10 ? ? ?
+C AMD bull ? ? ?
+C AMD pile ? ? ?
+C AMD steam ? ? ?
+C AMD bobcat ? ? ?
+C AMD jaguar ? ? ?
+C Intel P4 ? ? ?
+C Intel core ? ? ?
+C Intel NHM ? ? ?
+C Intel SBR 2.57 2.93 3.0
+C Intel IBR 2.35 2.66 3.0
+C Intel HWL 2.02 2.5 2.5
+C Intel BWL ? ? ?
+C Intel atom ? ? ?
+C VIA nano ? ? ?
+
+C The inner loops of this code are the result of running a code generation and
+C optimisation tool suite written by David Harvey and Torbjörn Granlund, except
+C that the sqr_diag_addlsh1 loop was manually written.
+
+C TODO
+C * Replace current unoptimised sqr_diag_addlsh1 loop, 2.5 c/l should be easy.
+C * Streamline pointer updates.
+C * Perhaps suppress a few more xor insns in feed-in code.
+C * Make sure we write no dead registers in feed-in code.
+C * We might use 32-bit size ops, since n >= 2^32 is non-terminating. Watch
+C out for negative sizes being zero-extended, though.
+C * The straight-line code for n <= 3 comes from the K8 code, and might be
+C quite sub-optimal here. Write specific code, and add code for n = 4.
+C * The mul_2 loop has a 10 insn common sequence in the loop start and the
+C wind-down code. Try re-rolling it.
+C * This file has been the subject to just basic micro-optimisation.
+
+C When playing with pointers, set this to $2 to fall back to conservative
+C indexing in wind-down code.
+define(`I',`$1')
+
+define(`rp', `%rdi')
+define(`up', `%rsi')
+define(`un_param',`%rdx')
+
+
+ABI_SUPPORT(DOS64)
+ABI_SUPPORT(STD64)
+
+ASM_START()
+ TEXT
+ ALIGN(32)
+PROLOGUE(mpn_sqr_basecase)
+ FUNC_ENTRY(3)
+
+ cmp $2, un_param
+ jae L(gt1)
+
+ mov (up), %rax
+ mul %rax
+ mov %rax, (rp)
+ mov %rdx, 8(rp)
+ FUNC_EXIT()
+ ret
+
+L(gt1): jne L(gt2)
+
+ mov (up), %rax
+ mov %rax, %r8
+ mul %rax
+ mov 8(up), %r11
+ mov %rax, (rp)
+ mov %r11, %rax
+ mov %rdx, %r9
+ mul %rax
+ mov %rax, %r10
+ mov %r11, %rax
+ mov %rdx, %r11
+ mul %r8
+ xor %r8, %r8
+ add %rax, %r9
+ adc %rdx, %r10
+ adc %r8, %r11
+ add %rax, %r9
+ mov %r9, 8(rp)
+ adc %rdx, %r10
+ mov %r10, 16(rp)
+ adc %r8, %r11
+ mov %r11, 24(rp)
+ FUNC_EXIT()
+ ret
+
+L(gt2): cmp $4, un_param
+ jae L(gt3)
+define(`v0', `%r8')
+define(`v1', `%r9')
+define(`w0', `%r10')
+define(`w2', `%r11')
+
+ mov (up), %rax
+ mov %rax, %r10
+ mul %rax
+ mov 8(up), %r11
+ mov %rax, (rp)
+ mov %r11, %rax
+ mov %rdx, 8(rp)
+ mul %rax
+ mov 16(up), %rcx
+ mov %rax, 16(rp)
+ mov %rcx, %rax
+ mov %rdx, 24(rp)
+ mul %rax
+ mov %rax, 32(rp)
+ mov %rdx, 40(rp)
+
+ mov %r11, %rax
+ mul %r10
+ mov %rax, %r8
+ mov %rcx, %rax
+ mov %rdx, %r9
+ mul %r10
+ xor %r10, %r10
+ add %rax, %r9
+ mov %r11, %rax
+ mov %r10, %r11
+ adc %rdx, %r10
+
+ mul %rcx
+ add %rax, %r10
+ adc %r11, %rdx
+ add %r8, %r8
+ adc %r9, %r9
+ adc %r10, %r10
+ adc %rdx, %rdx
+ adc %r11, %r11
+ add %r8, 8(rp)
+ adc %r9, 16(rp)
+ adc %r10, 24(rp)
+ adc %rdx, 32(rp)
+ adc %r11, 40(rp)
+ FUNC_EXIT()
+ ret
+
+L(gt3):
+
+define(`v0', `%r8')
+define(`v1', `%r9')
+define(`w0', `%r10')
+define(`w1', `%r11')
+define(`w2', `%rbx')
+define(`w3', `%rbp')
+define(`un', `%r12')
+define(`n', `%rcx')
+
+define(`X0', `%r13')
+define(`X1', `%r14')
+
+L(do_mul_2):
+ mov (up), v0
+ push %rbx
+ lea (rp,un_param,8), rp C point rp at R[un]
+ mov 8(up), %rax
+ push %rbp
+ lea (up,un_param,8), up C point up right after U's end
+ mov %rax, v1
+ push %r12
+ mov $1, R32(un) C free up rdx
+ push %r13
+ sub un_param, un
+ push %r14
+ push un
+ mul v0
+ mov %rax, (rp,un,8)
+ mov 8(up,un,8), %rax
+ test $1, R8(un)
+ jnz L(m2b1)
+
+L(m2b0):lea 2(un), n
+ xor R32(w2), R32(w2) C FIXME
+ xor R32(w1), R32(w1) C FIXME
+ mov %rdx, w0
+ jmp L(m2l0)
+
+L(m2b1):lea 1(un), n
+ xor R32(w0), R32(w0) C FIXME
+ xor R32(w3), R32(w3) C FIXME
+ mov %rdx, w2
+ jmp L(m2l1)
+
+ ALIGN(32)
+L(m2tp):
+L(m2l0):mul v0
+ add %rax, w0 C 1
+ mov %rdx, w3 C 2
+ adc $0, w3 C 2
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