[Gmp-commit] /var/hg/gmp: 5 new changesets
mercurial at gmplib.org
mercurial at gmplib.org
Thu Aug 15 17:02:43 CEST 2013
details: /var/hg/gmp/rev/49912d2c67c4
changeset: 15927:49912d2c67c4
user: Torbjorn Granlund <tege at gmplib.org>
date: Thu Aug 15 16:59:22 2013 +0200
description:
Provide Haswell sqr_basecase. Not perfectly tuned wrt O(n) and O(1).
details: /var/hg/gmp/rev/52d41bb6b981
changeset: 15928:52d41bb6b981
user: Torbjorn Granlund <tege at gmplib.org>
date: Thu Aug 15 17:01:16 2013 +0200
description:
Cycle table update.
details: /var/hg/gmp/rev/5b9c3012043d
changeset: 15929:5b9c3012043d
user: Torbjorn Granlund <tege at gmplib.org>
date: Thu Aug 15 17:01:39 2013 +0200
description:
Cycle table update.
details: /var/hg/gmp/rev/7c713850193f
changeset: 15930:7c713850193f
user: Torbjorn Granlund <tege at gmplib.org>
date: Thu Aug 15 17:02:00 2013 +0200
description:
Add a TODO item.
details: /var/hg/gmp/rev/932c9d20bab5
changeset: 15931:932c9d20bab5
user: Torbjorn Granlund <tege at gmplib.org>
date: Thu Aug 15 17:02:32 2013 +0200
description:
ChangeLog
diffstat:
ChangeLog | 8 +
mpn/x86_64/coreihwl/mulx/mul_2.asm | 3 +
mpn/x86_64/coreihwl/mulx/sqr_basecase.asm | 474 ++++++++++++++++++++++++++++++
mpn/x86_64/coreisbr/addmul_2.asm | 2 +-
mpn/x86_64/coreisbr/mul_2.asm | 6 +-
5 files changed, 489 insertions(+), 4 deletions(-)
diffs (truncated from 534 to 300 lines):
diff -r a658ab80f7b6 -r 932c9d20bab5 ChangeLog
--- a/ChangeLog Mon Aug 05 13:18:00 2013 +0200
+++ b/ChangeLog Thu Aug 15 17:02:32 2013 +0200
@@ -1,3 +1,11 @@
+2013-08-15 Torbjorn Granlund <tege at gmplib.org>
+
+ * mpn/x86_64/coreihwl/mulx/sqr_basecase.asm: New file.
+
+2013-08-05 Torbjorn Granlund <tege at gmplib.org>
+
+ * mpn/x86_64/coreisbr/aors_n.asm: Complete rewrite.
+
2013-08-04 Torbjorn Granlund <tege at gmplib.org>
* mpn/x86_64/coreihwl/mulx/mul_basecase.asm: New file.
diff -r a658ab80f7b6 -r 932c9d20bab5 mpn/x86_64/coreihwl/mulx/mul_2.asm
--- a/mpn/x86_64/coreihwl/mulx/mul_2.asm Mon Aug 05 13:18:00 2013 +0200
+++ b/mpn/x86_64/coreihwl/mulx/mul_2.asm Thu Aug 15 17:02:32 2013 +0200
@@ -42,6 +42,9 @@
C The loop of this code is the result of running a code generation and
C optimisation tool suite written by David Harvey and Torbjörn Granlund.
+C TODO
+C * Move test and jcc together, for insn fusion.
+
define(`rp', `%rdi')
define(`up', `%rsi')
define(`n_param',`%rdx')
diff -r a658ab80f7b6 -r 932c9d20bab5 mpn/x86_64/coreihwl/mulx/sqr_basecase.asm
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mpn/x86_64/coreihwl/mulx/sqr_basecase.asm Thu Aug 15 17:02:32 2013 +0200
@@ -0,0 +1,474 @@
+dnl AMD64 mpn_sqr_basecase optimised for Intel Haswell.
+
+dnl Contributed to the GNU project by Torbjörn Granlund.
+
+dnl Copyright 2008, 2009, 2011, 2012, 2013 Free Software Foundation, Inc.
+
+dnl This file is part of the GNU MP Library.
+
+dnl The GNU MP Library is free software; you can redistribute it and/or modify
+dnl it under the terms of the GNU Lesser General Public License as published
+dnl by the Free Software Foundation; either version 3 of the License, or (at
+dnl your option) any later version.
+
+dnl The GNU MP Library is distributed in the hope that it will be useful, but
+dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+dnl License for more details.
+
+dnl You should have received a copy of the GNU Lesser General Public License
+dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/.
+
+include(`../config.m4')
+
+C cycles/limb mul_2 addmul_2 sqr_diag_addlsh1
+C AMD K8,K9 n/a n/a n/a
+C AMD K10 n/a n/a n/a
+C AMD bull n/a n/a n/a
+C AMD pile n/a n/a n/a
+C AMD steam ? ? ?
+C AMD bobcat n/a n/a n/a
+C AMD jaguar ? ? ?
+C Intel P4 n/a n/a n/a
+C Intel core n/a n/a n/a
+C Intel NHM n/a n/a n/a
+C Intel SBR n/a n/a n/a
+C Intel IBR n/a n/a n/a
+C Intel HWL 1.86 2.15 ?
+C Intel BWL ? ? ?
+C Intel atom n/a n/a n/a
+C VIA nano n/a n/a n/a
+
+C The inner loops of this code are the result of running a code generation and
+C optimisation tool suite written by David Harvey and Torbjörn Granlund, except
+C that the sqr_diag_addlsh1 loop was manually written.
+
+C TODO
+C * Streamline pointer updates.
+C * Perhaps suppress a few more xor insns in feed-in code.
+C * Implement larger "corner", perhaps much larger.
+C * We might use 32-bit size ops, since n >= 2^32 is non-terminating.
+C Watch out for negative sizes being zero-extended, though.
+
+define(`rp', `%rdi')
+define(`up', `%rsi')
+define(`un_param',`%rdx')
+
+
+ABI_SUPPORT(DOS64)
+ABI_SUPPORT(STD64)
+
+ASM_START()
+ TEXT
+ ALIGN(32)
+PROLOGUE(mpn_sqr_basecase)
+ FUNC_ENTRY(3)
+
+ cmp $2, un_param
+ jae L(gt1)
+
+ mov (up), %rdx
+ mulx %rdx, %rax, %rdx
+ mov %rax, (rp)
+ mov %rdx, 8(rp)
+ FUNC_EXIT()
+ ret
+
+L(gt1): jne L(gt2)
+
+ mov (up), %rdx
+ mov 8(up), %rcx
+ mulx %rcx, %r9, %r10 C v0 * v1 W 1 2
+ mulx %rdx, %rax, %r8 C v0 * v0 W 0 1
+ mov %rcx, %rdx
+ mulx %rdx, %r11, %rdx C v1 * v1 W 2 3
+ add %r9, %r9 C W 1
+ adc %r10, %r10 C W 2
+ adc $0, %rdx C W 3
+ add %r9, %r8 C W 1
+ adc %r11, %r10 C W 2
+ adc $0, %rdx C W 3
+ mov %rax, (rp)
+ mov %r8, 8(rp)
+ mov %r10, 16(rp)
+ mov %rdx, 24(rp)
+ FUNC_EXIT()
+ ret
+
+L(gt2):
+ cmp $4, un_param
+ jae L(gt3)
+define(`v0', `%r8')
+define(`v1', `%r9')
+define(`w0', `%r10')
+define(`w2', `%r11')
+
+ mov (up), v0
+ mov 8(up), v1
+ mov v1, %rdx
+ mulx v0, w2, %rax
+ mov 16(up), %rdx
+ mulx v0, w0, %rcx
+ mov w2, %r8
+ add %rax, w0
+ adc $0, %rcx
+ mulx v1, %rdx, %rax
+ add %rcx, %rdx
+ mov %rdx, 24(rp)
+ adc $0, %rax
+ mov %rax, 32(rp)
+ xor R32(%rcx), R32(%rcx)
+ mov (up), %rdx
+ mulx %rdx, %rax, w2
+ mov %rax, (rp)
+ add %r8, %r8
+ adc w0, w0
+ setc R8(%rcx)
+ mov 8(up), %rdx
+ mulx %rdx, %rax, %rdx
+ add w2, %r8
+ adc %rax, w0
+ mov %r8, 8(rp)
+ mov w0, 16(rp)
+ mov 24(rp), %r8
+ mov 32(rp), w0
+ lea (%rdx,%rcx), w2
+ adc %r8, %r8
+ adc w0, w0
+ setc R8(%rcx)
+ mov 16(up), %rdx
+ mulx %rdx, %rax, %rdx
+ add w2, %r8
+ adc %rax, w0
+ mov %r8, 24(rp)
+ mov w0, 32(rp)
+ adc %rcx, %rdx
+ mov %rdx, 40(rp)
+ FUNC_EXIT()
+ ret
+L(gt3):
+
+define(`v0', `%r8')
+define(`v1', `%r9')
+define(`w0', `%r10')
+define(`w1', `%r11')
+define(`w2', `%rbx')
+define(`w3', `%rbp')
+define(`un', `%r12')
+define(`n', `%rcx')
+
+define(`X0', `%r13')
+define(`X1', `%r14')
+
+
+ push %rbx
+ push %rbp
+ push %r12
+ push %r13
+ push %r14
+ mov un_param, un C free up rdx
+ neg un
+ push un
+ lea 8(up), up C offset up (for now)
+
+L(do_mul_2):
+ mov -8(up), v0
+ mov (up), v1
+ lea 8(rp), rp
+
+ lea 2(un), n
+ sar $2, n
+ inc un C decrement |un|
+
+ mov v1, %rdx
+ test $1, R8(un)
+ jnz L(mx1)
+
+L(mx0): mulx v0, w2, w1
+ mov 8(up), %rdx
+ mov w2, (rp)
+ xor w2, w2
+ mulx v0, w0, w3
+ test $2, R8(un)
+ jz L(mlo0)
+
+L(m10): lea -16(rp), rp
+ lea -16(up), up
+ jmp L(mlo2)
+
+L(mx1): mulx v0, w0, w3
+ mov 8(up), %rdx
+ mov w0, (rp)
+ xor w0, w0
+ test $2, R8(un)
+ mulx v0, w2, w1
+ jz L(m11)
+
+L(m01): lea 8(rp), rp
+ lea 8(up), up
+ jmp L(mlo1)
+
+L(m11): lea -8(rp), rp
+ lea -8(up), up
+ jmp L(mlo3)
+
+ ALIGN(32)
+L(mtop):mulx v1, %rax, w0
+ add %rax, w2 C 0
+ mov (up), %rdx
+ mulx v0, %rax, w1
+ adc $0, w0 C 1
+ add %rax, w2 C 0
+L(mlo1):adc $0, w1 C 1
+ add w3, w2 C 0
+ mov w2, (rp) C 0
+ adc $0, w1 C 1
+ mulx v1, %rax, w2
+ add %rax, w0 C 1
+ mov 8(up), %rdx
+ adc $0, w2 C 2
+ mulx v0, %rax, w3
+ add %rax, w0 C 1
+ adc $0, w3 C 2
+L(mlo0):add w1, w0 C 1
+ mov w0, 8(rp) C 1
+ adc $0, w3 C 2
+ mulx v1, %rax, w0
+ add %rax, w2 C 2
+ mov 16(up), %rdx
+ mulx v0, %rax, w1
+ adc $0, w0 C 3
+ add %rax, w2 C 2
+ adc $0, w1 C 3
+L(mlo3):add w3, w2 C 2
+ mov w2, 16(rp) C 2
+ adc $0, w1 C 3
+ mulx v1, %rax, w2
+ add %rax, w0 C 3
+ mov 24(up), %rdx
+ adc $0, w2 C 4
+ mulx v0, %rax, w3
+ add %rax, w0 C 3
+ adc $0, w3 C 4
+L(mlo2):add w1, w0 C 3
+ lea 32(up), up
+ mov w0, 24(rp) C 3
+ adc $0, w3 C 4
+ inc n
+ lea 32(rp), rp
+ jnz L(mtop)
+
+L(mend):mulx v1, %rdx, %rax
+ add %rdx, w2
+ adc $0, %rax
+ add w3, w2
+ mov w2, (rp)
+ adc $0, %rax
+ mov %rax, 8(rp)
+
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