[Gmp-commit] /var/hg/gmp: 5 new changesets

mercurial at gmplib.org mercurial at gmplib.org
Mon Apr 29 00:48:18 CEST 2013


details:   /var/hg/gmp/rev/b5d7bddc74a1
changeset: 15759:b5d7bddc74a1
user:      Torbjorn Granlund <tege at gmplib.org>
date:      Mon Apr 29 00:18:48 2013 +0200
description:
Fix a typo.

details:   /var/hg/gmp/rev/df1377f552e1
changeset: 15760:df1377f552e1
user:      Torbjorn Granlund <tege at gmplib.org>
date:      Mon Apr 29 00:33:32 2013 +0200
description:
(sparc-*-*): Recognise t5 along with t3 and t4.
Remove sparc64/ultrasparct1 from path_64 for T3, T3, and T5.

details:   /var/hg/gmp/rev/224adfd1a557
changeset: 15761:224adfd1a557
user:      Torbjorn Granlund <tege at gmplib.org>
date:      Mon Apr 29 00:46:33 2013 +0200
description:
Override mpn_addlsh1_n, mpn_addlsh2_n, mpn_sublsh1_n, etc with mpn_addlsh_n, etc when !HAVE_NATIVE the former but HAVE_NATIVE the latter.

details:   /var/hg/gmp/rev/f84c4b95ad98
changeset: 15762:f84c4b95ad98
user:      Torbjorn Granlund <tege at gmplib.org>
date:      Mon Apr 29 00:47:36 2013 +0200
description:
Add SPARC T3 addlsh_n and sublsh_n.

details:   /var/hg/gmp/rev/93f57985d570
changeset: 15763:93f57985d570
user:      Torbjorn Granlund <tege at gmplib.org>
date:      Mon Apr 29 00:48:14 2013 +0200
description:
ChangeLog

diffstat:

 ChangeLog                              |   11 ++
 configure.ac                           |   14 +-
 gmp-impl.h                             |   40 +++++++++
 mpn/sparc64/ultrasparct3/aorslsh_n.asm |  136 +++++++++++++++++++++++++++++++++
 mpn/sparc64/ultrasparct3/mod_1_4.asm   |    2 +-
 5 files changed, 195 insertions(+), 8 deletions(-)

diffs (279 lines):

diff -r ae7de7fcd44b -r 93f57985d570 ChangeLog
--- a/ChangeLog	Sat Apr 27 01:57:43 2013 +0200
+++ b/ChangeLog	Mon Apr 29 00:48:14 2013 +0200
@@ -1,3 +1,14 @@
+2013-04-29  Torbjorn Granlund  <tege at gmplib.org>
+
+	* gmp-impl.h: Override mpn_addlsh1_n, mpn_addlsh2_n, mpn_sublsh1_n, etc
+	with mpn_addlsh_n, etc when !HAVE_NATIVE the former but HAVE_NATIVE the
+	latter.
+
+	* mpn/sparc64/ultrasparct3/aorslsh_n.asm: New file.
+
+	* configure.ac (sparc-*-*): Recognise t5 along with t3 and t4.
+	Remove sparc64/ultrasparct1 from path_64 for T3, T3, and T5.
+
 2013-04-27  Mike Frysinger  <vapier at gentoo.org>
 
 	* configure.ac (arm*-*-*): Set up path also for plainest CPU varaints.
diff -r ae7de7fcd44b -r 93f57985d570 configure.ac
--- a/configure.ac	Sat Apr 27 01:57:43 2013 +0200
+++ b/configure.ac	Mon Apr 29 00:48:14 2013 +0200
@@ -1293,7 +1293,7 @@
         path="sparc32/v8/supersparc sparc32/v8 sparc32" ;;
       [sparc64 | sparcv9* | ultrasparc | ultrasparc[234]*])
         path="sparc32/v9 sparc32/v8 sparc32" ;;
-      [ultrasparct[1234]])
+      [ultrasparct[12345]])
         path="sparc32/ultrasparct1 sparc32/v8 sparc32" ;;
       *)
         path="sparc32" ;;
@@ -1314,7 +1314,7 @@
     # abilist="64" only.
     #
     case $host_cpu in
-      [ultrasparct[34]])
+      [ultrasparct[345]])
         gcc_32_cflags="$gcc_cflags -Wa,-xarch=v8plusd" ;;
       sparc64 | sparcv9* | ultrasparc*)
         gcc_32_cflags="$gcc_cflags -Wa,-xarch=v8plus" ;;
@@ -1356,7 +1356,7 @@
 	case $host_cpu in
 	  sparcv8 | microsparc | supersparc | turbosparc)
 					      cc_cflags_arch="-xarch=v8" ;;
-          [ultrasparct[34]])                  cc_cflags_arch="-xarch=v8plusd" ;;
+          [ultrasparct[345]])                 cc_cflags_arch="-xarch=v8plusd" ;;
 	  sparc64 | sparcv9* | ultrasparc*)   cc_cflags_arch="-xarch=v8plus" ;;
 	  *)                                  cc_cflags_arch="-xarch=v7" ;;
 	esac
@@ -1415,8 +1415,8 @@
 	    path_64="sparc64/ultrasparc34 sparc64/ultrasparc1234 sparc64" ;;
 	  [ultrasparct[12]])
 	    path_64="sparc64/ultrasparct1 sparc64" ;;
-	  [ultrasparct[34]])
-	    path_64="sparc64/ultrasparct3 sparc64/ultrasparct1 sparc64" ;;
+	  [ultrasparct[345]])
+	    path_64="sparc64/ultrasparct3 sparc64" ;;
 	  *)
 	    path_64="sparc64"
 	esac
@@ -1440,7 +1440,7 @@
         gcc_64_cflags_optlist="cpu"
 
 	case $host_cpu in
-          [ultrasparct[34]])
+          [ultrasparct[345]])
             gcc_64_cflags="$gcc_64_cflags -Wa,-xarch=v9d" ;;
         esac
 
@@ -1455,7 +1455,7 @@
             cclist_64="$cclist_64 cc"
             cc_64_cflags_optlist="cpu"
             case $host_cpu in
-              [ultrasparct[34]])
+              [ultrasparct[345]])
                 cc_64_cflags="$cc_64_cflags -xO3 -xarch=v9d" ;;
               *)
                 cc_64_cflags="-xO3 -xarch=v9" ;;
diff -r ae7de7fcd44b -r 93f57985d570 gmp-impl.h
--- a/gmp-impl.h	Sat Apr 27 01:57:43 2013 +0200
+++ b/gmp-impl.h	Mon Apr 29 00:48:14 2013 +0200
@@ -1566,6 +1566,46 @@
 __GMP_DECLSPEC void mpn_sbpi1_div_r_sec (mp_ptr, mp_size_t, mp_srcptr, mp_size_t, mp_limb_t, mp_ptr);
 
 
+/* Override mpn_addlsh1_n, mpn_addlsh2_n, mpn_sublsh1_n, etc with mpn_addlsh_n,
+   etc when !HAVE_NATIVE the former but HAVE_NATIVE_ the latter.  */
+
+#if HAVE_NATIVE_mpn_addlsh_n && ! HAVE_NATIVE_mpn_addlsh1_n
+#undef mpn_addlsh1_n
+#define mpn_addlsh1_n(a,b,c,d) mpn_addlsh_n(a,b,c,d,1)
+#define HAVE_NATIVE_mpn_addlsh1_n 1
+#endif
+
+#if HAVE_NATIVE_mpn_addlsh_n && ! HAVE_NATIVE_mpn_addlsh2_n
+#undef mpn_addlsh2_n
+#define mpn_addlsh2_n(a,b,c,d) mpn_addlsh_n(a,b,c,d,2)
+#define HAVE_NATIVE_mpn_addlsh2_n 1
+#endif
+
+#if HAVE_NATIVE_mpn_sublsh_n && ! HAVE_NATIVE_mpn_sublsh1_n
+#undef mpn_sublsh1_n
+#define mpn_sublsh1_n(a,b,c,d) mpn_sublsh_n(a,b,c,d,1)
+#define HAVE_NATIVE_mpn_sublsh1_n 1
+#endif
+
+#if HAVE_NATIVE_mpn_sublsh_n && ! HAVE_NATIVE_mpn_sublsh2_n
+#undef mpn_sublsh2_n
+#define mpn_sublsh2_n(a,b,c,d) mpn_sublsh_n(a,b,c,d,2)
+#define HAVE_NATIVE_mpn_sublsh2_n 1
+#endif
+
+#if HAVE_NATIVE_mpn_rsblsh_n && ! HAVE_NATIVE_mpn_rsblsh1_n
+#undef mpn_rsblsh1_n
+#define mpn_rsblsh1_n(a,b,c,d) mpn_rsblsh_n(a,b,c,d,1)
+#define HAVE_NATIVE_mpn_rsblsh1_n 1
+#endif
+
+#if HAVE_NATIVE_mpn_rsblsh_n && ! HAVE_NATIVE_mpn_rsblsh2_n
+#undef mpn_rsblsh2_n
+#define mpn_rsblsh2_n(a,b,c,d) mpn_rsblsh_n(a,b,c,d,2)
+#define HAVE_NATIVE_mpn_rsblsh2_n 1
+#endif
+
+
 #ifndef DIVEXACT_BY3_METHOD
 #if GMP_NUMB_BITS % 2 == 0 && ! defined (HAVE_NATIVE_mpn_divexact_by3c)
 #define DIVEXACT_BY3_METHOD 0	/* default to using mpn_bdiv_dbm1c */
diff -r ae7de7fcd44b -r 93f57985d570 mpn/sparc64/ultrasparct3/aorslsh_n.asm
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mpn/sparc64/ultrasparct3/aorslsh_n.asm	Mon Apr 29 00:48:14 2013 +0200
@@ -0,0 +1,136 @@
+dnl  SPARC v9 mpn_addlsh_n and mpn_sublsh_n for T3/T4/T5.
+
+dnl  Contributed to the GNU project by Torbjörn Granlund.
+
+dnl  Copyright 2013 Free Software Foundation, Inc.
+
+dnl  This file is part of the GNU MP Library.
+
+dnl  The GNU MP Library is free software; you can redistribute it and/or modify
+dnl  it under the terms of the GNU Lesser General Public License as published
+dnl  by the Free Software Foundation; either version 3 of the License, or (at
+dnl  your option) any later version.
+
+dnl  The GNU MP Library is distributed in the hope that it will be useful, but
+dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
+dnl  License for more details.
+
+dnl  You should have received a copy of the GNU Lesser General Public License
+dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.
+
+include(`../config.m4')
+
+C		   cycles/limb
+C UltraSPARC T3:	 ?
+C UltraSPARC T4:	 4 c/l hopefully
+
+C For sublsh_n we combine the two shifted limbs using xnor, using the identity
+C (a xor not b) = (not (a xor b)) which equals (not (a or b)) when (a and b) =
+C 0 as it is in our usage.  This gives us the ones complement for free.
+C Unfortunately, the same trick will not work for rsblsh_n, which will instead
+C require a separate negation.
+C
+C FIXME: Add rsblsh_n to this file.
+
+define(`rp', `%i0')
+define(`up', `%i1')
+define(`vp', `%i2')
+define(`n',  `%i3')
+define(`cnt',`%i4')
+
+define(`tnc',`%o5')
+
+ifdef(`OPERATION_addlsh_n',`
+  define(`INITCY', `subcc	%g0, 0, %g0')
+  define(`MERGE', `or')
+  define(`func',  `mpn_addlsh_n')
+')
+ifdef(`OPERATION_sublsh_n',`
+  define(`INITCY', `subcc	%g0, 1, %g0')
+  define(`MERGE',  `xnor')
+  define(`func',  `mpn_sublsh_n')
+')
+
+define(`rp0',  `rp')
+define(`rp1',  `%o2')
+define(`up0',  `up')
+define(`up1',  `%o3')
+define(`vp0',  `vp')
+define(`vp1',  `%o4')
+
+MULFUNC_PROLOGUE(mpn_addlsh_n mpn_sublsh_n)
+ASM_START()
+	REGISTER(%g2,#scratch)
+	REGISTER(%g3,#scratch)
+PROLOGUE(func)
+	save	%sp, -176, %sp
+	INITCY
+	mov	64, tnc
+	sub	tnc, cnt, tnc
+
+	andcc	n, 1, %g0
+	sllx	n, 3, n
+	add	n, -16, n
+	add	up, n, up0
+	add	vp, n, vp0
+	add	rp, n, rp0
+	add	up0, 8, up1
+	add	vp0, 8, vp1
+	add	rp0, -8, rp1
+	add	rp0, -16, rp0
+	be	L(evn)
+	 neg	n
+
+L(odd):	ldx	[vp0 + n], %l1
+	mov	0, %l2
+	ldx	[up0 + n], %l5
+	sllx	%l1, cnt, %g3
+	brgez	n, L(wd1)
+	 add	n, 8, n
+	ldx	[vp0 + n], %l0
+	b	L(lo1)
+	 sllx	%l1, cnt, %g3
+
+L(evn):	ldx	[vp0 + n], %l0
+	mov	0, %l3
+	ldx	[up0 + n], %l4
+	ldx	[vp1 + n], %l1
+	b	L(lo0)
+	 sllx	%l0, cnt, %g1
+
+L(top):	addxccc(%l6, %l4, %o0)
+	ldx	[vp0 + n], %l0
+	sllx	%l1, cnt, %g3
+	stx	%o0, [rp0 + n]
+L(lo1):	srlx	%l1, tnc, %l3
+	MERGE	%l2, %g3, %l7
+	ldx	[up0 + n], %l4
+	addxccc(%l7, %l5, %o1)
+	ldx	[vp1 + n], %l1
+	sllx	%l0, cnt, %g1
+	stx	%o1, [rp1 + n]
+L(lo0):	srlx	%l0, tnc, %l2
+	MERGE	%l3, %g1, %l6
+	ldx	[up1 + n], %l5
+	brlz,pt	n, L(top)
+	 add	n, 16, n
+
+	addxccc(%l6, %l4, %o0)
+	sllx	%l1, cnt, %g3
+	stx	%o0, [rp0 + n]
+L(wd1):	srlx	%l1, tnc, %l3
+	MERGE	%l2, %g3, %l7
+	addxccc(%l7, %l5, %o1)
+	stx	%o1, [rp1 + n]
+
+ifdef(`OPERATION_addlsh_n',
+`	addxc(	%l3, %g0, %i0)')
+ifdef(`OPERATION_sublsh_n',
+`	addxc(	%g0, %g0, %g1)
+	add	%g1, -1, %g1
+	sub	%l3, %g1, %i0')
+
+	ret
+	 restore
+EPILOGUE()
diff -r ae7de7fcd44b -r 93f57985d570 mpn/sparc64/ultrasparct3/mod_1_4.asm
--- a/mpn/sparc64/ultrasparct3/mod_1_4.asm	Sat Apr 27 01:57:43 2013 +0200
+++ b/mpn/sparc64/ultrasparct3/mod_1_4.asm	Mon Apr 29 00:48:14 2013 +0200
@@ -191,7 +191,7 @@
 	mulx	%g1, %o0, %g1
 	cmp	%g1, %g3
 	add	%i1, %g3, %g2
-	movgeu	%xcc, %g3, %2
+	movgeu	%xcc, %g3, %g2
 	srlx	%g2, %i5, %g1
 	stx	%g1, [%i0+32]
 


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