[Gmp-commit] /var/hg/gmp: Sparc symbol handling overhaul.
mercurial at gmplib.org
mercurial at gmplib.org
Wed Apr 10 22:42:38 CEST 2013
details: /var/hg/gmp/rev/ace68333a9dc
changeset: 15705:ace68333a9dc
user: David S. Miller
date: Wed Apr 10 22:42:33 2013 +0200
description:
Sparc symbol handling overhaul.
diffstat:
ChangeLog | 18 ++++++
acinclude.m4 | 51 +++++++++++++++++
configure.ac | 4 +-
mpn/sparc32/sparc-defs.m4 | 94 ++++++++++++++++++++++++++++++++
mpn/sparc32/udiv.asm | 21 +-----
mpn/sparc32/v8/addmul_1.asm | 12 +---
mpn/sparc32/v8/mul_1.asm | 12 +---
mpn/sparc32/v8/supersparc/udiv.asm | 22 +-----
mpn/sparc32/v8/udiv.asm | 22 +-----
mpn/sparc32/v9/sqr_diagonal.asm | 14 +---
mpn/sparc64/gcd_1.asm | 25 +-------
mpn/sparc64/ultrasparct3/dive_1.asm | 26 +-------
mpn/sparc64/ultrasparct3/invert_limb.asm | 6 +-
mpn/sparc64/ultrasparct3/mode1o.asm | 26 +-------
14 files changed, 204 insertions(+), 149 deletions(-)
diffs (truncated from 590 to 300 lines):
diff -r a51d8e63e08e -r ace68333a9dc ChangeLog
--- a/ChangeLog Tue Apr 09 15:05:39 2013 +0200
+++ b/ChangeLog Wed Apr 10 22:42:33 2013 +0200
@@ -1,3 +1,21 @@
+2013-04-10 David S. Miller <davem at davemloft.net>
+
+ * acinclude.m4 (GMP_ASM_SPARC_GOTDATA,
+ GMP_ASM_SPARC_SHARED_THUNKS): New feature tests.
+ * configure.ac: Call GMP_ASM_SPARC_GOTDATA and
+ GMP_ASM_SPARC_SHARED_THUNKS on sparc.
+ * mpn/sparc32/sparc-defs.m4 (LEA, LEA_LEAF, LEA_THUNK): New macros.
+ * mpn/sparc32/udiv.asm: Convert over to LEA, LEA_LEAF, and LEA_THUNK.
+ * mpn/sparc32/v8/addmul_1.asm: Likewise.
+ * mpn/sparc32/v8/mul_1.asm: Likewise.
+ * mpn/sparc32/v8/supersparc/udiv.asm: Likewise.
+ * mpn/sparc32/v8/udiv.asm: Likewise.
+ * mpn/sparc64/gcd_1.asm: Likewise.
+ * mpn/sparc64/ultrasparct3/dive_1.asm: Likewise.
+ * mpn/sparc64/ultrasparct3/invert_limb.asm: Likewise.
+ * mpn/sparc64/ultrasparct3/mode1o.asm: Likewise.
+ * mpn/sparc32/v9/sqr_diagonal.asm: Likewise and use INT32.
+
2013-04-09 Torbjorn Granlund <tege at gmplib.org>
* config.guess (sparc*): Invoke set_cc_for_build to get $dummy.
diff -r a51d8e63e08e -r ace68333a9dc acinclude.m4
--- a/acinclude.m4 Tue Apr 09 15:05:39 2013 +0200
+++ b/acinclude.m4 Wed Apr 10 22:42:33 2013 +0200
@@ -3090,6 +3090,57 @@
])
+dnl GMP_ASM_SPARC_GOTDATA
+dnl ----------------------
+dnl Determine whether the assembler accepts gotdata relocations.
+dnl
+dnl See also mpn/sparc32/sparc-defs.m4 which uses the result of this test.
+
+AC_DEFUN([GMP_ASM_SPARC_GOTDATA],
+[AC_REQUIRE([GMP_ASM_TEXT])
+AC_CACHE_CHECK([if the assembler accepts gotdata relocations],
+ gmp_cv_asm_sparc_gotdata,
+[GMP_TRY_ASSEMBLE(
+[ $gmp_cv_asm_text
+ .text
+ sethi %gdop_hix22(symbol), %g1
+ or %g1, %gdop_lox10(symbol), %g1
+],
+[gmp_cv_asm_sparc_gotdata=yes],
+[gmp_cv_asm_sparc_gotdata=no])])
+
+GMP_DEFINE_RAW(["define(<HAVE_GOTDATA>,<$gmp_cv_asm_sparc_gotdata>)"])
+])
+
+
+dnl GMP_ASM_SPARC_SHARED_THUNKS
+dnl ----------------------
+dnl Determine whether the assembler supports all of the features
+dnl necessary in order to emit shared PIC thunks on sparc.
+dnl
+dnl See also mpn/sparc32/sparc-defs.m4 which uses the result of this test.
+
+AC_DEFUN([GMP_ASM_SPARC_SHARED_THUNKS],
+[AC_REQUIRE([GMP_ASM_TEXT])
+AC_CACHE_CHECK([if the assembler can support shared PIC thunks],
+ gmp_cv_asm_sparc_shared_thunks,
+[GMP_TRY_ASSEMBLE(
+[ $gmp_cv_asm_text
+ .section .text.__sparc_get_pc_thunk.l7,"axG", at progbits,__sparc_get_pc_thunk.l7,comdat
+ .weak __sparc_get_pc_thunk.l7
+ .hidden __sparc_get_pc_thunk.l7
+ .type __sparc_get_pc_thunk.l7, #function
+__sparc_get_pc_thunk.l7:
+ jmp %o7+8
+ add %o7, %l7, %l7
+],
+[gmp_cv_asm_sparc_shared_thunks=yes],
+[gmp_cv_asm_sparc_shared_thunks=no])])
+
+GMP_DEFINE_RAW(["define(<HAVE_SHARED_THUNKS>,<$gmp_cv_asm_sparc_shared_thunks>)"])
+])
+
+
dnl GMP_C_ATTRIBUTE_CONST
dnl ---------------------
diff -r a51d8e63e08e -r ace68333a9dc configure.ac
--- a/configure.ac Tue Apr 09 15:05:39 2013 +0200
+++ b/configure.ac Wed Apr 10 22:42:33 2013 +0200
@@ -3483,12 +3483,14 @@
power*-*-aix*)
GMP_INCLUDE_MPN(powerpc32/aix.m4)
;;
- sparcv9*-*-* | ultrasparc*-*-* | sparc64-*-*)
+ *sparc*-*-*)
case $ABI in
64)
GMP_ASM_SPARC_REGISTER
;;
esac
+ GMP_ASM_SPARC_GOTDATA
+ GMP_ASM_SPARC_SHARED_THUNKS
;;
X86_PATTERN | X86_64_PATTERN)
GMP_ASM_ALIGN_FILL_0x90
diff -r a51d8e63e08e -r ace68333a9dc mpn/sparc32/sparc-defs.m4
--- a/mpn/sparc32/sparc-defs.m4 Tue Apr 09 15:05:39 2013 +0200
+++ b/mpn/sparc32/sparc-defs.m4 Wed Apr 10 22:42:33 2013 +0200
@@ -35,6 +35,100 @@
`ifelse(HAVE_REGISTER,yes,
`.register `$1',`$2'')')
+dnl Usage: LEA(symbol,reg,pic_reg)
+dnl
+dnl Use whatever code sequence is appropriate to load "symbol" into register
+dnl "reg", potentially using register "pic_reg" to perform the calculations.
+dnl This takes into consideration things like PIC, whether we are generating
+dnl 64-bit code, etc.
+
+define(LEA,
+m4_assert_numargs(3)
+m4_assert_defined(`HAVE_GOTDATA')
+`ifdef(`PIC',`
+ifelse(HAVE_GOTDATA,yes,`
+ sethi %hi(_GLOBAL_OFFSET_TABLE_-4), %`$3'
+ call __sparc_get_pc_thunk.`$3'
+ or %`$3', %lo(_GLOBAL_OFFSET_TABLE_+4), %`$3'
+99: sethi %gdop_hix22(`$1'), %`$2'
+ xor %`$2', %gdop_lox10(`$1'), %`$2'
+ifdef(`HAVE_ABI_64',`
+ ldx [%`$3' + %`$2'], %`$2', %gdop(`$1')',`
+ ld [%`$3' + %`$2'], %`$2', %gdop(`$1')')',`
+ sethi %hi(_GLOBAL_OFFSET_TABLE_-4), %`$3'
+ call __sparc_get_pc_thunk.`$3'
+ or %`$3', %lo(_GLOBAL_OFFSET_TABLE_+4), %`$3'
+99: sethi %hi(`$1'), %`$2'
+ or %`$2', %lo(`$1'), %`$2'
+ifdef(`HAVE_ABI_64',`
+ ldx [%`$3' + %`$2'], %`$2'',`
+ ld [%`$3' + %`$2'], %`$2'')')',`
+ifdef(`HAVE_ABI_64',`
+ setx `$1', %`$3', %`$2'',`
+ set `$1', %`$2'')')')
+
+dnl Usage: LEA_LEAF(symbol,reg,pic_reg)
+dnl
+dnl Exactly the same as LEA except that it works in a leaf function.
+dnl Specifically, when generating PIC code, it makes sure to preserve the %o7
+dnl register.
+
+define(LEA_LEAF,
+m4_assert_numargs(3)
+m4_assert_defined(`HAVE_GOTDATA')
+`ifdef(`PIC',`
+ifelse(HAVE_GOTDATA,yes,`
+ sethi %hi(_GLOBAL_OFFSET_TABLE_-4), %`$3'
+ mov %o7, %`$2'
+ call __sparc_get_pc_thunk.`$3'
+ or %`$3', %lo(_GLOBAL_OFFSET_TABLE_+4), %`$3'
+99: mov %`$2', %o7
+ sethi %gdop_hix22(`$1'), %`$2'
+ xor %`$2', %gdop_lox10(`$1'), %`$2'
+ifdef(`HAVE_ABI_64',`
+ ldx [%`$3' + %`$2'], %`$2', %gdop(`$1')',`
+ ld [%`$3' + %`$2'], %`$2', %gdop(`$1')')',`
+ sethi %hi(_GLOBAL_OFFSET_TABLE_-4), %`$3'
+ mov %o7, %`$2'
+ call __sparc_get_pc_thunk.`$3'
+ or %`$3', %lo(_GLOBAL_OFFSET_TABLE_+4), %`$3'
+99: mov %`$2', %o7
+ sethi %hi(`$1'), %`$2'
+ or %`$2', %lo(`$1'), %`$2'
+ifdef(`HAVE_ABI_64',`
+ ldx [%`$3' + %`$2'], %`$2'',`
+ ld [%`$3' + %`$2'], %`$2'')')',`
+ifdef(`HAVE_ABI_64',`
+ setx `$1', %`$3', %`$2'',`
+ set `$1', %`$2'')')')
+
+dnl Usage: LEA_THUNK(pic_reg)
+dnl
+dnl Files that make use of LEA and LEA_LEAF must emit a PIC thunk using
+dnl LEA_THUNK. The "pic_reg" argument given must exactly the same as the
+dnl one given to the LEA LEA_LEAF invocations.
+dnl
+dnl If multiple PIC registers are used in invocations of LEA and LEA_LEAF then
+dnl multiple thunks needs to be emitted, one for each PIC register used.
+
+define(LEA_THUNK,
+m4_assert_numargs(1)
+m4_assert_defined(`HAVE_SHARED_THUNKS')
+`ifdef(`PIC',`
+ifelse(HAVE_SHARED_THUNKS,yes,`
+ .section .text.__sparc_get_pc_thunk.`$1',"axG", at progbits,__sparc_get_pc_thunk.`$1',comdat
+ .weak __sparc_get_pc_thunk.`$1'
+ .hidden __sparc_get_pc_thunk.`$1'
+ .type __sparc_get_pc_thunk.`$1', #function
+__sparc_get_pc_thunk.`$1':
+ jmp %o7+8
+ add %o7, %`$1', %`$1'
+ TEXT
+',`
+ TEXT
+__sparc_get_pc_thunk.`$1':
+ retl
+ add %o7, %`$1', %`$1'')')')
C Testing mechanism for running newer code on older processors
ifdef(`FAKE_T3',`
diff -r a51d8e63e08e -r ace68333a9dc mpn/sparc32/udiv.asm
--- a/mpn/sparc32/udiv.asm Tue Apr 09 15:05:39 2013 +0200
+++ b/mpn/sparc32/udiv.asm Wed Apr 10 22:42:33 2013 +0200
@@ -28,13 +28,7 @@
C d i3
ASM_START()
-
-ifdef(`PIC',
-` TEXT
-L(getpc):
- retl
- nop')
-
+ LEA_THUNK(l7)
TEXT
ALIGN(8)
L(C0): .double 0r4294967296
@@ -45,11 +39,8 @@
st %i1,[%fp-8]
ld [%fp-8],%f10
-ifdef(`PIC',
-`L(pc): call L(getpc) C put address of this insn in %o7
- ldd [%o7+L(C0)-L(pc)],%f8',
-` sethi %hi(L(C0)),%o7
- ldd [%o7+%lo(L(C0))],%f8')
+ LEA(L(C0),l0,l7)
+ ldd [%l0], %f8
fitod %f10,%f4
cmp %i1,0
@@ -75,10 +66,8 @@
L(250):
fdivd %f2,%f4,%f2
-ifdef(`PIC',
-` ldd [%o7+L(C1)-L(pc)],%f4',
-` sethi %hi(L(C1)),%o7
- ldd [%o7+%lo(L(C1))],%f4')
+ LEA(L(C1),l0,l7)
+ ldd [%l0], %f4
fcmped %f2,%f4
nop
diff -r a51d8e63e08e -r ace68333a9dc mpn/sparc32/v8/addmul_1.asm
--- a/mpn/sparc32/v8/addmul_1.asm Tue Apr 09 15:05:39 2013 +0200
+++ b/mpn/sparc32/v8/addmul_1.asm Wed Apr 10 22:42:33 2013 +0200
@@ -28,21 +28,15 @@
C s2_limb o3
ASM_START()
+ LEA_THUNK(g4)
+ TEXT
PROLOGUE(mpn_addmul_1)
orcc %g0,%g0,%g2
ld [%o1+0],%o4 C 1
sll %o2,4,%g1
and %g1,(4-1)<<4,%g1
-ifdef(`PIC',
-` mov %o7,%g4 C Save return address register
-0: call 1f
- add %o7,L(1)-0b,%g3
-1: mov %g4,%o7 C Restore return address register
-',
-` sethi %hi(L(1)),%g3
- or %g3,%lo(L(1)),%g3
-')
+ LEA_LEAF(L(1),g3,g4)
jmp %g3+%g1
nop
L(1):
diff -r a51d8e63e08e -r ace68333a9dc mpn/sparc32/v8/mul_1.asm
--- a/mpn/sparc32/v8/mul_1.asm Tue Apr 09 15:05:39 2013 +0200
+++ b/mpn/sparc32/v8/mul_1.asm Wed Apr 10 22:42:33 2013 +0200
@@ -28,18 +28,12 @@
C s2_limb o3
ASM_START()
+ LEA_THUNK(g4)
+ TEXT
PROLOGUE(mpn_mul_1)
sll %o2,4,%g1
and %g1,(4-1)<<4,%g1
-ifdef(`PIC',
-` mov %o7,%g4 C Save return address register
-0: call 1f
- add %o7,L(1)-0b,%g3
-1: mov %g4,%o7 C Restore return address register
-',
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