[Gmp-commit] /var/hg/gmp: 6 new changesets
mercurial at gmplib.org
mercurial at gmplib.org
Wed Nov 9 22:36:02 CET 2011
details: /var/hg/gmp/rev/cea8d89498d1
changeset: 14425:cea8d89498d1
user: Torbjorn Granlund <tege at gmplib.org>
date: Wed Nov 09 16:34:21 2011 +0100
description:
Fix comment typo.
details: /var/hg/gmp/rev/1994ae507012
changeset: 14426:1994ae507012
user: Torbjorn Granlund <tege at gmplib.org>
date: Wed Nov 09 22:26:07 2011 +0100
description:
(gmp_mpn_functions): Add addcnd_n and subcnd_n.
details: /var/hg/gmp/rev/368e41f2ce45
changeset: 14427:368e41f2ce45
user: Torbjorn Granlund <tege at gmplib.org>
date: Wed Nov 09 22:29:36 2011 +0100
description:
New file.
details: /var/hg/gmp/rev/589d13b4d06b
changeset: 14428:589d13b4d06b
user: Torbjorn Granlund <tege at gmplib.org>
date: Wed Nov 09 22:31:09 2011 +0100
description:
Add measuring of mpn_addcnd_n, mpn_subcnd_n.
details: /var/hg/gmp/rev/56d6bcf6e739
changeset: 14429:56d6bcf6e739
user: Torbjorn Granlund <tege at gmplib.org>
date: Wed Nov 09 22:31:54 2011 +0100
description:
Add testing of mpn_addcnd_n, mpn_subcnd_n.
details: /var/hg/gmp/rev/414814f291ed
changeset: 14430:414814f291ed
user: Torbjorn Granlund <tege at gmplib.org>
date: Wed Nov 09 22:32:44 2011 +0100
description:
Declare just added refmpn_addcnd_n, refmpn_subcnd_n.
diffstat:
configure.in | 1 +
mpn/powerpc64/mode64/mul_basecase.asm | 2 +-
mpn/powerpc64/mode64/p6/mul_basecase.asm | 2 +-
mpn/x86_64/aorscnd_n.asm | 164 +++++++++++++++++++++++++++++++
tests/devel/try.c | 16 +++
tests/refmpn.c | 23 ++++
tests/tests.h | 5 +
tune/common.c | 11 ++
tune/speed.c | 3 +
tune/speed.h | 2 +
10 files changed, 227 insertions(+), 2 deletions(-)
diffs (truncated from 345 to 300 lines):
diff -r a3fa4d967de2 -r 414814f291ed configure.in
--- a/configure.in Mon Nov 07 18:42:54 2011 +0100
+++ b/configure.in Wed Nov 09 22:32:44 2011 +0100
@@ -2654,6 +2654,7 @@
tmp_mulfunc="aors_err2_n" ;;
add_err3_n|sub_err3_n)
tmp_mulfunc="aors_err3_n" ;;
+ addcnd_n|subcnd_n) tmp_mulfunc="aorscnd_n" ;;
addmul_1|submul_1) tmp_mulfunc="aorsmul_1" ;;
popcount|hamdist) tmp_mulfunc="popham" ;;
and_n|andn_n|nand_n | ior_n|iorn_n|nior_n | xor_n|xnor_n)
diff -r a3fa4d967de2 -r 414814f291ed mpn/powerpc64/mode64/mul_basecase.asm
--- a/mpn/powerpc64/mode64/mul_basecase.asm Mon Nov 07 18:42:54 2011 +0100
+++ b/mpn/powerpc64/mode64/mul_basecase.asm Wed Nov 09 22:32:44 2011 +0100
@@ -1,4 +1,4 @@
-dnl PowerPC-64 mpn_basecase.
+dnl PowerPC-64 mpn_mul_basecase.
dnl Copyright 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2008 Free Software
dnl Foundation, Inc.
diff -r a3fa4d967de2 -r 414814f291ed mpn/powerpc64/mode64/p6/mul_basecase.asm
--- a/mpn/powerpc64/mode64/p6/mul_basecase.asm Mon Nov 07 18:42:54 2011 +0100
+++ b/mpn/powerpc64/mode64/p6/mul_basecase.asm Wed Nov 09 22:32:44 2011 +0100
@@ -1,4 +1,4 @@
-dnl PowerPC-64 mpn_basecase.
+dnl PowerPC-64 mpn_mul_basecase.
dnl Copyright 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2008, 2010 Free
dnl Software Foundation, Inc.
diff -r a3fa4d967de2 -r 414814f291ed mpn/x86_64/aorscnd_n.asm
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mpn/x86_64/aorscnd_n.asm Wed Nov 09 22:32:44 2011 +0100
@@ -0,0 +1,164 @@
+dnl AMD64 mpn_addcnd_n, mpn_subcnd_n
+
+dnl Copyright 2011 Free Software Foundation, Inc.
+
+dnl This file is part of the GNU MP Library.
+
+dnl The GNU MP Library is free software; you can redistribute it and/or modify
+dnl it under the terms of the GNU Lesser General Public License as published
+dnl by the Free Software Foundation; either version 3 of the License, or (at
+dnl your option) any later version.
+
+dnl The GNU MP Library is distributed in the hope that it will be useful, but
+dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+dnl License for more details.
+
+dnl You should have received a copy of the GNU Lesser General Public License
+dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/.
+
+include(`../config.m4')
+
+C cycles/limb
+C AMD K8,K9 2.25
+C AMD K10 2
+C Intel P4 13
+C Intel core2 2.9
+C Intel NHM 2.9
+C Intel SBR 2.4
+C Intel atom 6.5
+C VIA nano 3
+
+C NOTES
+C * It might seem natural to use the cmov insn here, but since this function
+C is supposed to have the exact same execution pattern for cnd true and
+C false, and since cmov's documentation is not clear about wheather it
+C actually reads both source operands and writes the register for a false
+C condition, we cannot use it.
+C * Two cases could be optimised: (1) addcnd_n could use ADCSBB-from-memory
+C to save one insn/limb, and (2) when up=rp addcnd_n and subcnd_n could use
+C ADCSBB-to-memory, again saving 1 insn/limb.
+C * This runs optimally at decoder bandwidth on K10. It has not been tuned
+C for any other processor.
+
+C INPUT PARAMETERS
+define(`rp', `%rdi')
+define(`up', `%rsi')
+define(`vp', `%rdx')
+define(`n', `%rcx')
+define(`cnd', `%r8')
+
+ifdef(`OPERATION_addcnd_n', `
+ define(ADDSUB, add)
+ define(ADCSBB, adc)
+ define(func, mpn_addcnd_n)')
+ifdef(`OPERATION_subcnd_n', `
+ define(ADDSUB, sub)
+ define(ADCSBB, sbb)
+ define(func, mpn_subcnd_n)')
+
+MULFUNC_PROLOGUE(mpn_addcnd_n mpn_subcnd_n)
+
+ASM_START()
+ TEXT
+ ALIGN(16)
+PROLOGUE(func)
+ push %rbx
+ push %rbp
+ push %r12
+ push %r13
+ push %r14
+
+ neg cnd
+ sbb cnd, cnd C make cnd mask
+
+ lea (vp,n,8), vp
+ lea (up,n,8), up
+ lea (rp,n,8), rp
+
+ mov R32(n), R32(%rax)
+ neg n
+ and $3, R32(%rax)
+ jz L(top) C carry-save reg rax = 0 in this arc
+ cmp $2, R32(%rax)
+ jc L(b1)
+ jz L(b2)
+
+L(b3): mov (vp,n,8), %r12
+ mov 8(vp,n,8), %r13
+ mov 16(vp,n,8), %r14
+ mov (up,n,8), %r10
+ mov 8(up,n,8), %rbx
+ mov 16(up,n,8), %rbp
+ and cnd, %r12
+ and cnd, %r13
+ and cnd, %r14
+ ADDSUB %r12, %r10
+ ADCSBB %r13, %rbx
+ ADCSBB %r14, %rbp
+ sbb R32(%rax), R32(%rax) C save carry
+ mov %r10, (rp,n,8)
+ mov %rbx, 8(rp,n,8)
+ mov %rbp, 16(rp,n,8)
+ add $3, n
+ js L(top)
+ jmp L(end)
+
+L(b2): mov (vp,n,8), %r12
+ mov 8(vp,n,8), %r13
+ mov (up,n,8), %r10
+ mov 8(up,n,8), %rbx
+ and cnd, %r12
+ and cnd, %r13
+ ADDSUB %r12, %r10
+ ADCSBB %r13, %rbx
+ sbb R32(%rax), R32(%rax) C save carry
+ mov %r10, (rp,n,8)
+ mov %rbx, 8(rp,n,8)
+ add $2, n
+ js L(top)
+ jmp L(end)
+
+L(b1): mov (vp,n,8), %r12
+ mov (up,n,8), %r10
+ and cnd, %r12
+ ADDSUB %r12, %r10
+ sbb R32(%rax), R32(%rax) C save carry
+ mov %r10, (rp,n,8)
+ add $1, n
+ jns L(end)
+
+ ALIGN(16)
+L(top): mov (vp,n,8), %r12
+ mov 8(vp,n,8), %r13
+ mov 16(vp,n,8), %r14
+ mov 24(vp,n,8), %r11
+ mov (up,n,8), %r10
+ mov 8(up,n,8), %rbx
+ mov 16(up,n,8), %rbp
+ mov 24(up,n,8), %r9
+ and cnd, %r12
+ and cnd, %r13
+ and cnd, %r14
+ and cnd, %r11
+ add R32(%rax), R32(%rax) C restore carry
+ ADCSBB %r12, %r10
+ ADCSBB %r13, %rbx
+ ADCSBB %r14, %rbp
+ ADCSBB %r11, %r9
+ sbb R32(%rax), R32(%rax) C save carry
+ mov %r10, (rp,n,8)
+ mov %rbx, 8(rp,n,8)
+ mov %rbp, 16(rp,n,8)
+ mov %r9, 24(rp,n,8)
+ add $4, n
+ js L(top)
+
+L(end): neg R32(%rax)
+ pop %r14
+ pop %r13
+ pop %r12
+ pop %rbp
+ pop %rbx
+ ret
+EPILOGUE()
diff -r a3fa4d967de2 -r 414814f291ed tests/devel/try.c
--- a/tests/devel/try.c Mon Nov 07 18:42:54 2011 +0100
+++ b/tests/devel/try.c Wed Nov 09 22:32:44 2011 +0100
@@ -622,6 +622,8 @@
TYPE_SUBLSH1_NC, TYPE_SUBLSH2_NC, TYPE_SUBLSH_NC,
TYPE_RSBLSH1_NC, TYPE_RSBLSH2_NC, TYPE_RSBLSH_NC,
+ TYPE_ADDCND_N, TYPE_SUBCND_N,
+
TYPE_MOD_1, TYPE_MOD_1C, TYPE_DIVMOD_1, TYPE_DIVMOD_1C, TYPE_DIVREM_1,
TYPE_DIVREM_1C, TYPE_PREINV_DIVREM_1, TYPE_DIVREM_2, TYPE_PREINV_MOD_1,
TYPE_MOD_34LSUB1, TYPE_UDIV_QRNND, TYPE_UDIV_QRNND_R,
@@ -742,6 +744,16 @@
COPY (TYPE_ADD_ERR3_N);
REFERENCE (refmpn_sub_err3_n);
+ p = ¶m[TYPE_ADDCND_N];
+ COPY (TYPE_ADD_N);
+ p->carry = CARRY_BIT;
+ REFERENCE (refmpn_addcnd_n);
+
+ p = ¶m[TYPE_SUBCND_N];
+ COPY (TYPE_ADD_N);
+ p->carry = CARRY_BIT;
+ REFERENCE (refmpn_subcnd_n);
+
p = ¶m[TYPE_MUL_1];
p->retval = 1;
@@ -1704,6 +1716,8 @@
{ TRY(mpn_copyd), TYPE_COPYD },
#endif
+ { TRY(mpn_addcnd_n), TYPE_ADDCND_N },
+ { TRY(mpn_subcnd_n), TYPE_SUBCND_N },
#if HAVE_NATIVE_mpn_addlsh1_n
{ TRY(mpn_addlsh1_n), TYPE_ADDLSH1_N },
#endif
@@ -2395,6 +2409,8 @@
case TYPE_RSBLSH2_NC:
case TYPE_ADD_NC:
case TYPE_SUB_NC:
+ case TYPE_ADDCND_N:
+ case TYPE_SUBCND_N:
e->retval = CALLING_CONVENTIONS (function)
(e->d[0].p, e->s[0].p, e->s[1].p, size, carry);
break;
diff -r a3fa4d967de2 -r 414814f291ed tests/refmpn.c
--- a/tests/refmpn.c Mon Nov 07 18:42:54 2011 +0100
+++ b/tests/refmpn.c Wed Nov 09 22:32:44 2011 +0100
@@ -596,6 +596,29 @@
return refmpn_sub_nc (rp, s1p, s2p, size, CNST_LIMB(0));
}
+mp_limb_t
+refmpn_addcnd_n (mp_ptr rp, mp_srcptr s1p, mp_srcptr s2p, mp_size_t size, mp_limb_t cnd)
+{
+ if (cnd != 0)
+ return refmpn_add_n (rp, s1p, s2p, size);
+ else
+ {
+ refmpn_copyi (rp, s1p, size);
+ return 0;
+ }
+}
+mp_limb_t
+refmpn_subcnd_n (mp_ptr rp, mp_srcptr s1p, mp_srcptr s2p, mp_size_t size, mp_limb_t cnd)
+{
+ if (cnd != 0)
+ return refmpn_sub_n (rp, s1p, s2p, size);
+ else
+ {
+ refmpn_copyi (rp, s1p, size);
+ return 0;
+ }
+}
+
#define AORS_ERR1_N(operation) \
{ \
diff -r a3fa4d967de2 -r 414814f291ed tests/tests.h
--- a/tests/tests.h Mon Nov 07 18:42:54 2011 +0100
+++ b/tests/tests.h Wed Nov 09 22:32:44 2011 +0100
@@ -172,6 +172,11 @@
mpf_srcptr n, mpf_srcptr d));
+mp_limb_t refmpn_addcnd_n __GMP_PROTO ((mp_ptr wp, mp_srcptr xp, mp_srcptr yp,
+ mp_size_t size, mp_limb_t cnd));
+mp_limb_t refmpn_subcnd_n __GMP_PROTO ((mp_ptr wp, mp_srcptr xp, mp_srcptr yp,
+ mp_size_t size, mp_limb_t cnd));
+
mp_limb_t refmpn_add __GMP_PROTO ((mp_ptr rp,
mp_srcptr s1p, mp_size_t s1size,
mp_srcptr s2p, mp_size_t s2size));
diff -r a3fa4d967de2 -r 414814f291ed tune/common.c
--- a/tune/common.c Mon Nov 07 18:42:54 2011 +0100
+++ b/tune/common.c Wed Nov 09 22:32:44 2011 +0100
@@ -1107,6 +1107,17 @@
}
#endif
+double
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