[Gmp-commit] /var/hg/gmp: 2 new changesets

[mercurial at gmplib.org]

details:   /var/hg/gmp/rev/c09ef2c6b55d
changeset: 14094:c09ef2c6b55d
user:      Torbjorn Granlund <tege at gmplib.org>
date:      Tue Mar 22 15:04:12 2011 +0100
description:
Disable powerpc asm for _LONG_LONG_LIMB.

details:   /var/hg/gmp/rev/4aeb0b693420
changeset: 14095:4aeb0b693420
user:      Torbjorn Granlund <tege at gmplib.org>
date:      Tue Mar 22 15:04:44 2011 +0100
description:
*** empty log message ***

diffstat:

 ChangeLog              |  9 +++++++++
 mpn/generic/div_qr_2.c |  6 +++++-
 mpn/generic/mod_1_1.c  |  6 +++++-
 3 files changed, 19 insertions(+), 2 deletions(-)

diffs (60 lines):

diff -r 07fda551b831 -r 4aeb0b693420 ChangeLog
--- a/ChangeLog	Tue Mar 22 14:51:38 2011 +0100
+++ b/ChangeLog	Tue Mar 22 15:04:44 2011 +0100
@@ -1,3 +1,12 @@
+2011-03-22  Torbjorn Granlund  <tege at gmplib.org>
+
+	* mpn/generic/mod_1_1.c: Disable powerpc asm for _LONG_LONG_LIMB.
+	* mpn/generic/div_qr_2.c: Likewise.
+
+	* mpn/generic/div_qr_2.c: Use asm just for gcc.
+	Make powerpc add_sssaaaa work for 32-bit case, and use less strict
+	constraints.
+
 2011-03-21  Niels Möller  <nisse at lysator.liu.se>
 
 	* tune/tuneup.c (div_qr_2_pi2_threshold): New global variable.
diff -r 07fda551b831 -r 4aeb0b693420 mpn/generic/div_qr_2.c
--- a/mpn/generic/div_qr_2.c	Tue Mar 22 14:51:38 2011 +0100
+++ b/mpn/generic/div_qr_2.c	Tue Mar 22 15:04:44 2011 +0100
@@ -76,12 +76,16 @@
 	     "%1" ((UDItype)(a)), "g" ((UDItype)(b)))
 #endif
 
-#if HAVE_HOST_CPU_FAMILY_powerpc
+#if HAVE_HOST_CPU_FAMILY_powerpc && !defined (_LONG_LONG_LIMB)
+/* This works fine for 32-bit and 64-bit limbs, except for 64-bit limbs with a
+   processor running in 32-bit mode, since the carry flag then gets the 32-bit
+   carry.  */
 #define add_sssaaaa(s2, s1, s0, a1, a0, b1, b0)				\
   __asm__ ("add%I7c\t%2,%6,%7\n\tadde\t%1,%4,%5\n\taddze\t%0,%0"	\
 	   : "=r" (s2), "=&r" (s1), "=&r" (s0)				\
 	   : "r"  (s2), "r"  (a1), "r" (b1), "%r" (a0), "rI" (b0))
 #endif
+
 #endif /* __GNUC__ */
 
 #ifndef add_sssaaaa
diff -r 07fda551b831 -r 4aeb0b693420 mpn/generic/mod_1_1.c
--- a/mpn/generic/mod_1_1.c	Tue Mar 22 14:51:38 2011 +0100
+++ b/mpn/generic/mod_1_1.c	Tue Mar 22 15:04:44 2011 +0100
@@ -82,7 +82,10 @@
 	 __CLOBBER_CC)
 #endif
 
-#if HAVE_HOST_CPU_FAMILY_powerpc  /* should work fine for 32-bit and 64-bit */
+#if HAVE_HOST_CPU_FAMILY_powerpc && !defined (_LONG_LONG_LIMB)
+/* This works fine for 32-bit and 64-bit limbs, except for 64-bit limbs with a
+   processor running in 32-bit mode, since the carry flag then gets the 32-bit
+   carry.  */
 #define add_mssaaaa(m, s1, s0, a1, a0, b1, b0)				\
   __asm__ (  "add%I6c	%2, %5, %6\n\t"					\
 	     "adde	%1, %3, %4\n\t"					\
@@ -93,6 +96,7 @@
 #endif
 #endif /* defined (__GNUC__) */
 
+
 #if defined (__arm__) && W_TYPE_SIZE == 32
 #define add_mssaaaa(m, sh, sl, ah, al, bh, bl)				\
   __asm__ (  "adds	%2, %5, %6\n\t"					\