[Gmp-commit] /home/hgfiles/gmp: 5 new changesets
mercurial at gmplib.org
mercurial at gmplib.org
Sat May 8 00:50:50 CEST 2010
details: /home/hgfiles/gmp/rev/b31a2d64385a
changeset: 13613:b31a2d64385a
user: Torbjorn Granlund <tege at gmplib.org>
date: Fri May 07 21:12:21 2010 +0200
description:
New file.
details: /home/hgfiles/gmp/rev/8d3c44a86cc1
changeset: 13614:8d3c44a86cc1
user: Torbjorn Granlund <tege at gmplib.org>
date: Fri May 07 21:14:38 2010 +0200
description:
Support operands of >= 2^32 limbs.
details: /home/hgfiles/gmp/rev/5f7f7a1f2c5b
changeset: 13615:5f7f7a1f2c5b
user: Torbjorn Granlund <tege at gmplib.org>
date: Sat May 08 00:45:53 2010 +0200
description:
Provide aorslsh1_n and aorslsh2_n using same mechanism.
details: /home/hgfiles/gmp/rev/d8872b3c0c97
changeset: 13616:d8872b3c0c97
user: Torbjorn Granlund <tege at gmplib.org>
date: Sat May 08 00:49:04 2010 +0200
description:
Disable mpn_rsh1add_n, mpn_rsh1sub_n for Atom.
details: /home/hgfiles/gmp/rev/d9d303fcd120
changeset: 13617:d9d303fcd120
user: Torbjorn Granlund <tege at gmplib.org>
date: Sat May 08 00:50:30 2010 +0200
description:
Minor cleanup.
diffstat:
ChangeLog | 12 ++
mpn/powerpc64/mode64/aorslsh1_n.asm | 6 -
mpn/powerpc64/mode64/aorslsh2_n.asm | 6 -
mpn/powerpc64/mode64/aorslshC_n.asm | 2 -
mpn/sparc64/add_n.asm | 10 +-
mpn/sparc64/addmul_1.asm | 10 +-
mpn/sparc64/copyd.asm | 8 +-
mpn/sparc64/copyi.asm | 8 +-
mpn/sparc64/gmp-mparam.h | 7 +-
mpn/sparc64/lshift.asm | 36 +++---
mpn/sparc64/lshiftc.asm | 155 ++++++++++++++++++++++++++++
mpn/sparc64/mul_1.asm | 10 +-
mpn/sparc64/rshift.asm | 36 +++---
mpn/sparc64/sub_n.asm | 10 +-
mpn/sparc64/ultrasparc34/gmp-mparam.h | 5 +-
mpn/x86_64/atom/gmp-mparam.h | 5 +
mpn/x86_64/pentium4/aorslsh1_n.asm | 166 +-----------------------------
mpn/x86_64/pentium4/aorslsh2_n.asm | 37 ++++++
mpn/x86_64/pentium4/aorslshC_n.asm | 188 ++++++++++++++++++++++++++++++++++
mpn/x86_64/pentium4/gmp-mparam.h | 1 -
20 files changed, 467 insertions(+), 251 deletions(-)
diffs (truncated from 1172 to 300 lines):
diff -r 4016f37871e8 -r d9d303fcd120 ChangeLog
--- a/ChangeLog Fri May 07 00:41:24 2010 +0200
+++ b/ChangeLog Sat May 08 00:50:30 2010 +0200
@@ -1,5 +1,17 @@
+2010-05-08 Torbjorn Granlund <tege at gmplib.org>
+
+ * mpn/x86_64/atom/gmp-mparam.h: Disable mpn_rsh1add_n, mpn_rsh1sub_n.
+
+ * mpn/x86_64/pentium4/aorslshC_n.asm: New file based on aorslsh1_n.asm.
+ * mpn/x86_64/pentium4/aorslsh1_n.asm: Just include aorslshC_n.asm.
+ * mpn/x86_64/pentium4/aorslsh2_n.asm: New file.
+
2010-05-07 Torbjorn Granlund <tege at gmplib.org>
+ * mpn/sparc64: Support operands of >= 2^32 limbs.
+
+ * mpn/sparc64/lshiftc.asm: New file.
+
* mpn/ia64/divrem_2.asm: Complete rewrite.
2010-05-06 Torbjorn Granlund <tege at gmplib.org>
diff -r 4016f37871e8 -r d9d303fcd120 mpn/powerpc64/mode64/aorslsh1_n.asm
--- a/mpn/powerpc64/mode64/aorslsh1_n.asm Fri May 07 00:41:24 2010 +0200
+++ b/mpn/powerpc64/mode64/aorslsh1_n.asm Sat May 08 00:50:30 2010 +0200
@@ -19,11 +19,6 @@
include(`../config.m4')
-C cycles/limb
-C POWER3/PPC630: 1.83 (1.5 c/l should be possible)
-C POWER4/PPC970: 3 (2.0 c/l should be possible)
-C POWER5: 3
-
define(LSH, 1)
define(RSH, 63)
@@ -44,7 +39,6 @@
define(func, mpn_sublsh1_n)
')
-
MULFUNC_PROLOGUE(mpn_addlsh1_n mpn_sublsh1_n)
include_mpn(`powerpc64/mode64/aorslshC_n.asm')
diff -r 4016f37871e8 -r d9d303fcd120 mpn/powerpc64/mode64/aorslsh2_n.asm
--- a/mpn/powerpc64/mode64/aorslsh2_n.asm Fri May 07 00:41:24 2010 +0200
+++ b/mpn/powerpc64/mode64/aorslsh2_n.asm Sat May 08 00:50:30 2010 +0200
@@ -19,11 +19,6 @@
include(`../config.m4')
-C cycles/limb
-C POWER3/PPC630: 1.83 (1.5 c/l should be possible)
-C POWER4/PPC970: 3 (2.0 c/l should be possible)
-C POWER5: 3
-
define(LSH, 2)
define(RSH, 62)
@@ -44,7 +39,6 @@
define(func, mpn_sublsh2_n)
')
-
MULFUNC_PROLOGUE(mpn_addlsh2_n mpn_sublsh2_n)
include_mpn(`powerpc64/mode64/aorslshC_n.asm')
diff -r 4016f37871e8 -r d9d303fcd120 mpn/powerpc64/mode64/aorslshC_n.asm
--- a/mpn/powerpc64/mode64/aorslshC_n.asm Fri May 07 00:41:24 2010 +0200
+++ b/mpn/powerpc64/mode64/aorslshC_n.asm Sat May 08 00:50:30 2010 +0200
@@ -17,8 +17,6 @@
dnl You should have received a copy of the GNU Lesser General Public License
dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/.
-include(`../config.m4')
-
C cycles/limb
C POWER3/PPC630 1.83 (1.5 c/l should be possible)
C POWER4/PPC970 3 (2.0 c/l should be possible)
diff -r 4016f37871e8 -r d9d303fcd120 mpn/sparc64/add_n.asm
--- a/mpn/sparc64/add_n.asm Fri May 07 00:41:24 2010 +0200
+++ b/mpn/sparc64/add_n.asm Sat May 08 00:50:30 2010 +0200
@@ -59,7 +59,7 @@
fitod %f0,%f0 C make sure f0 contains small, quiet number
subcc n,4,%g0
- bl,pn %icc,.Loop0
+ bl,pn %xcc,.Loop0
mov 0,cy
ldx [up+0],u0
@@ -76,7 +76,7 @@
add u0,v0,%g1 C main add
add %g1,cy,%g4 C carry add
or u0,v0,%g2
- bl,pn %icc,.Lend4567
+ bl,pn %xcc,.Lend4567
fanop
b,a .Loop
@@ -159,7 +159,7 @@
C --
add %g1,cy,%g4
or u0,v0,%g2
- bge,pt %icc,.Loop
+ bge,pt %xcc,.Loop
fanop
C END MAIN LOOP
.Lend4567:
@@ -195,7 +195,7 @@
stx %g4,[rp-8]
addcc n,4,n
- bz,pn %icc,.Lret
+ bz,pn %xcc,.Lret
fanop
.Loop0: ldx [up],u0
@@ -211,7 +211,7 @@
andn %g2,%g4,%g2
stx %g4,[rp-8]
or %g3,%g2,%g2
- bnz,pt %icc,.Loop0
+ bnz,pt %xcc,.Loop0
srlx %g2,63,cy
.Lret: mov cy,%i0
diff -r 4016f37871e8 -r d9d303fcd120 mpn/sparc64/addmul_1.asm
--- a/mpn/sparc64/addmul_1.asm Fri May 07 00:41:24 2010 +0200
+++ b/mpn/sparc64/addmul_1.asm Sat May 08 00:50:30 2010 +0200
@@ -138,7 +138,7 @@
fmuld u32, v00, r32
fmuld u00, v48, p48
addcc %i2, 8, %i2
- bnz,pt %icc, .L_two_or_more
+ bnz,pt %xcc, .L_two_or_more
fmuld u32, v16, r48
.L_one:
@@ -216,7 +216,7 @@
faddd p16, r80, a16
fmuld u00, v48, p48
addcc %i2, 8, %i2
- bnz,pt %icc, .L_three_or_more
+ bnz,pt %xcc, .L_three_or_more
fmuld u32, v16, r48
.L_two:
@@ -298,7 +298,7 @@
faddd p16, r80, a16
fmuld u00, v48, p48
addcc %i2, 8, %i2
- bnz,pt %icc, .L_four_or_more
+ bnz,pt %xcc, .L_four_or_more
fmuld u32, v16, r48
.L_three:
@@ -386,7 +386,7 @@
fmuld u00, v48, p48
add cy, %g5, %o4 C x = prev(i00) + cy
addcc %i2, 8, %i2
- bnz,pt %icc, .Loop
+ bnz,pt %xcc, .Loop
fmuld u32, v16, r48
.L_four:
@@ -463,7 +463,7 @@
C 13
add cy, %g5, %o4 C x = prev(i00) + cy
addcc %i2, 8, %i2
- bnz,pt %icc, .Loop
+ bnz,pt %xcc, .Loop
fmuld u32, v16, r48
C END MAIN LOOP
diff -r 4016f37871e8 -r d9d303fcd120 mpn/sparc64/copyd.asm
--- a/mpn/sparc64/copyd.asm Fri May 07 00:41:24 2010 +0200
+++ b/mpn/sparc64/copyd.asm Sat May 08 00:50:30 2010 +0200
@@ -36,7 +36,7 @@
add %g1,%o0,%o0
add %g1,%o1,%o1
addcc %o2,-8,%o2
- bl,pt %icc,L(end01234567)
+ bl,pt %xcc,L(end01234567)
nop
L(loop1):
ldx [%o1-8],%g1
@@ -57,18 +57,18 @@
stx %o4,[%o0-56]
stx %o5,[%o0-64]
addcc %o2,-8,%o2
- bge,pt %icc,L(loop1)
+ bge,pt %xcc,L(loop1)
add %o0,-64,%o0
L(end01234567):
addcc %o2,8,%o2
- bz,pn %icc,L(end)
+ bz,pn %xcc,L(end)
nop
L(loop2):
ldx [%o1-8],%g1
add %o1,-8,%o1
addcc %o2,-1,%o2
stx %g1,[%o0-8]
- bg,pt %icc,L(loop2)
+ bg,pt %xcc,L(loop2)
add %o0,-8,%o0
L(end): retl
nop
diff -r 4016f37871e8 -r d9d303fcd120 mpn/sparc64/copyi.asm
--- a/mpn/sparc64/copyi.asm Fri May 07 00:41:24 2010 +0200
+++ b/mpn/sparc64/copyi.asm Sat May 08 00:50:30 2010 +0200
@@ -33,7 +33,7 @@
REGISTER(%g3,#scratch)
PROLOGUE(mpn_copyi)
addcc %o2,-8,%o2
- bl,pt %icc,L(end01234567)
+ bl,pt %xcc,L(end01234567)
nop
L(loop1):
ldx [%o1+0],%g1
@@ -54,18 +54,18 @@
stx %o4,[%o0+48]
stx %o5,[%o0+56]
addcc %o2,-8,%o2
- bge,pt %icc,L(loop1)
+ bge,pt %xcc,L(loop1)
add %o0,64,%o0
L(end01234567):
addcc %o2,8,%o2
- bz,pn %icc,L(end)
+ bz,pn %xcc,L(end)
nop
L(loop2):
ldx [%o1+0],%g1
add %o1,8,%o1
addcc %o2,-1,%o2
stx %g1,[%o0+0]
- bg,pt %icc,L(loop2)
+ bg,pt %xcc,L(loop2)
add %o0,8,%o0
L(end): retl
nop
diff -r 4016f37871e8 -r d9d303fcd120 mpn/sparc64/gmp-mparam.h
--- a/mpn/sparc64/gmp-mparam.h Fri May 07 00:41:24 2010 +0200
+++ b/mpn/sparc64/gmp-mparam.h Sat May 08 00:50:30 2010 +0200
@@ -28,12 +28,11 @@
#define MOD_1_NORM_THRESHOLD 3
#define MOD_1_UNNORM_THRESHOLD 3
#define MOD_1N_TO_MOD_1_1_THRESHOLD MP_SIZE_T_MAX /* never */
-#define MOD_1U_TO_MOD_1_1_THRESHOLD MP_SIZE_T_MAX
-#define MOD_1_1_TO_MOD_1_2_THRESHOLD MP_SIZE_T_MAX
-#define MOD_1_2_TO_MOD_1_4_THRESHOLD MP_SIZE_T_MAX
+#define MOD_1U_TO_MOD_1_1_THRESHOLD 22
+#define MOD_1_1_TO_MOD_1_2_THRESHOLD 0 /* never mpn_mod_1_1p */
+#define MOD_1_2_TO_MOD_1_4_THRESHOLD 27
#define PREINV_MOD_1_TO_MOD_1_THRESHOLD MP_SIZE_T_MAX /* never */
#define USE_PREINV_DIVREM_1 1
-#define DIVREM_2_THRESHOLD 7
#define DIVEXACT_1_THRESHOLD 0 /* always */
#define BMOD_1_TO_MOD_1_THRESHOLD MP_SIZE_T_MAX /* never */
diff -r 4016f37871e8 -r d9d303fcd120 mpn/sparc64/lshift.asm
--- a/mpn/sparc64/lshift.asm Fri May 07 00:41:24 2010 +0200
+++ b/mpn/sparc64/lshift.asm Sat May 08 00:50:30 2010 +0200
@@ -1,6 +1,7 @@
dnl SPARC v9 mpn_lshift
-dnl Copyright 1996, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+dnl Copyright 1996, 2000, 2001, 2002, 2003, 2010 Free Software Foundation,
+dnl Inc.
dnl This file is part of the GNU MP Library.
@@ -22,23 +23,22 @@
C cycles/limb
C UltraSPARC 1&2: 2
-C UltraSPARC 3: 3.25
+C UltraSPARC 3: 2.5
C INPUT PARAMETERS
-define(`rp',`%i0')
-define(`up',`%i1')
-define(`n',`%i2')
+define(`rp', `%i0')
+define(`up', `%i1')
+define(`n', `%i2')
define(`cnt',`%i3')
-define(`u0',`%l0')
-define(`u1',`%l2')
-define(`u2',`%l4')
-define(`u3',`%l6')
+define(`u0', `%l0')
+define(`u1', `%l2')
+define(`u2', `%l4')
+define(`u3', `%l6')
define(`tnc',`%i4')
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