x86-64 SIMD popcnt

[David Sparks]

On Wednesday, 7 October 2026 at 13:48, Torbjörn Granlund <tg at gmplib.org> wrote:
> I played with this back in 2021.  You might want to take a look at what
> I got:

Fun reading!  My detailed comments got lost in a power glitch,
but while I'm recreating this, I got the following working.

On my Haswell, I measure about 0.75 cycles/limb for that AVX2 code.

The attached Harley-Seal core achieves 0.5 cycles/limb for
L2-resident data.  Extending it to handle odd-sized
and unaligned buffers is a small matter of programming I'll
undertake if you're interested.

It's 5 instructions (plus one load, plus two moves if limited
to 2-operand instructions) per SIMD word.  Still a ways from
Haswell's theoretical 8 limbs/cycle L2 cache bandwidth, but
it's not too shabby.
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