add_ssaaaa and C++
Emmanuel Thomé
Emmanuel.Thome at inria.fr
Sun May 22 22:37:50 CEST 2005
On Sun, May 22, 2005 at 01:14:54PM +0200, Torbjorn Granlund wrote:
>
> I think this was made with the idea to make sure we'd get the
> right instruction variants even it the macro is fed with smaller
> types.
>
> But that reasoning really doesn't make sense. And we don't seem
> to be casting lvalues in other places in longlong.h.
> Furthermore, modern gcc pukes on code trying a non-noop lvalue
> cast:
>
> /home/tege/addas.c: In function `foo':
> /home/tege/addas.c:9: error: invalid lvalue in asm statement
> /home/tege/addas.c:9: error: invalid lvalue in asm statement
right. the nasty thing is that with g++, casting int& to long& in an asm
output, even though these types have the same width on i386, gives no
warning but produces rubbish code. Marvelous.
> I suggest this patch:
Actually, there are quite a few places where this feature is used (mostly
variants os add_ssaaa, but not only). So an extended patch would be along
the lines of the attached.
It seems to do the right thing, as the output has to have the right type.
Mismatch won't be caught by gcc, but it will be caught by the assembler,
provided the operations are properly qualified (addl vs add). I don't
know if each and every operation used enjoys this sort of type-checking.
E.
-------------- next part --------------
--- old/longlong.h 2005-01-16 20:07:25.000000000 +0100
+++ new/longlong.h 2005-05-21 13:22:03.000000000 +0200
@@ -319,16 +328,16 @@
#if defined (__arc__)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.f\t%1, %4, %5\n\tadc\t%0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "r" ((USItype) (ah)), \
"rIJ" ((USItype) (bh)), \
"%r" ((USItype) (al)), \
"rIJ" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.f\t%1, %4, %5\n\tsbc\t%0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "r" ((USItype) (ah)), \
"rIJ" ((USItype) (bh)), \
"r" ((USItype) (al)), \
@@ -476,21 +485,21 @@
#if defined (__gmicro__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.w %5,%1\n\taddx %3,%0" \
- : "=g" ((USItype)(sh)), "=&g" ((USItype)(sl)) \
+ : "=g" (sh), "=&g" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.w %5,%1\n\tsubx %3,%0" \
- : "=g" ((USItype)(sh)), "=&g" ((USItype)(sl)) \
+ : "=g" (sh), "=&g" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
#define umul_ppmm(ph, pl, m0, m1) \
__asm__ ("mulx %3,%0,%1" \
- : "=g" ((USItype)(ph)), "=r" ((USItype)(pl)) \
+ : "=g" (ph), "=r" (pl) \
: "%0" ((USItype)(m0)), "g" ((USItype)(m1)))
#define udiv_qrnnd(q, r, nh, nl, d) \
__asm__ ("divx %4,%0,%1" \
- : "=g" ((USItype)(q)), "=r" ((USItype)(r)) \
+ : "=g" (q), "=r" (r) \
: "1" ((USItype)(nh)), "0" ((USItype)(nl)), "g" ((USItype)(d)))
#define count_leading_zeros(count, x) \
__asm__ ("bsch/1 %1,%0" \
@@ -580,12 +593,12 @@
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl %5,%1\n\tadcl %3,%0" \
- : "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl %5,%1\n\tsbbl %3,%0" \
- : "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
#define umul_ppmm(w1, w0, u, v) \
@@ -711,12 +726,12 @@
#if defined (__x86_64__) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addq %5,%1\n\tadcq %3,%0" \
- : "=r" ((UDItype)(sh)), "=&r" ((UDItype)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "g" ((UDItype)(bh)), \
"%1" ((UDItype)(al)), "g" ((UDItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subq %5,%1\n\tsbbq %3,%0" \
- : "=r" ((UDItype)(sh)), "=&r" ((UDItype)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "g" ((UDItype)(bh)), \
"1" ((UDItype)(al)), "g" ((UDItype)(bl)))
#define umul_ppmm(w1, w0, u, v) \
@@ -803,12 +820,12 @@
|| defined (__mc5307__)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
- : "=d" ((USItype)(sh)), "=&d" ((USItype)(sl)) \
+ : "=d" (sh), "=&d" (sl) \
: "0" ((USItype)(ah)), "d" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
- : "=d" ((USItype)(sh)), "=&d" ((USItype)(sl)) \
+ : "=d" (sh), "=&d" (sl) \
: "0" ((USItype)(ah)), "d" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
@@ -819,17 +838,17 @@
|| defined (__NeXT__)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
- : "=d" ((USItype)(w0)), "=d" ((USItype)(w1)) \
+ : "=d" (w0), "=d" (w1) \
: "%0" ((USItype)(u)), "dmi" ((USItype)(v)))
#define UMUL_TIME 45
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divu%.l %4,%1:%0" \
- : "=d" ((USItype)(q)), "=d" ((USItype)(r)) \
+ : "=d" (q), "=d" (r) \
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "dmi" ((USItype)(d)))
#define UDIV_TIME 90
#define sdiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divs%.l %4,%1:%0" \
- : "=d" ((USItype)(q)), "=d" ((USItype)(r)) \
+ : "=d" (q), "=d" (r) \
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "dmi" ((USItype)(d)))
#else /* for other 68k family members use 16x16->32 multiplication */
#define umul_ppmm(xh, xl, a, b) \
@@ -874,7 +896,7 @@
&& ! defined (__mcpu32__)
#define count_leading_zeros(count, x) \
__asm__ ("bfffo %1{%b2:%b2},%0" \
- : "=d" ((USItype) (count)) \
+ : "=d" (count) \
: "od" ((USItype) (x)), "n" (0))
#define COUNT_LEADING_ZEROS_0 32
#endif
@@ -975,7 +997,7 @@
#define count_trailing_zeros(count,x) \
do { \
__asm__ ("ffsd %2,%0" \
- : "=r" ((USItype) (count)) \
+ : "=r" (count) \
: "0" ((USItype) 0), "r" ((USItype) (x))); \
} while (0)
#endif /* __ns32000__ */
@@ -1115,12 +1137,12 @@
#if defined (__pyr__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addw %5,%1\n\taddwc %3,%0" \
- : "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subw %5,%1\n\tsubwb %3,%0" \
- : "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
/* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
@@ -1137,12 +1161,12 @@
#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("a %1,%5\n\tae %0,%3" \
- : "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "r" ((USItype)(bh)), \
"%1" ((USItype)(al)), "r" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("s %1,%5\n\tse %0,%3" \
- : "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "r" ((USItype)(bh)), \
"1" ((USItype)(al)), "r" ((USItype)(bl)))
#define smul_ppmm(ph, pl, m0, m1) \
@@ -1167,7 +1193,7 @@
" m r2,%3\n" \
" cas %0,r2,r0\n" \
" mfs r10,%1" \
- : "=r" ((USItype)(ph)), "=r" ((USItype)(pl)) \
+ : "=r" (ph), "=r" (pl) \
: "%r" ((USItype)(m0)), "r" ((USItype)(m1)) \
: "r2")
#define UMUL_TIME 20
@@ -1176,11 +1203,11 @@
do { \
if ((x) >= 0x10000) \
__asm__ ("clz %0,%1" \
- : "=r" ((USItype)(count)) : "r" ((USItype)(x) >> 16)); \
+ : "=r" (count) : "r" ((USItype)(x) >> 16)); \
else \
{ \
__asm__ ("clz %0,%1" \
- : "=r" ((USItype)(count)) : "r" ((USItype)(x))); \
+ : "=r" (count) : "r" ((USItype)(x))); \
(count) += 16; \
} \
} while (0)
@@ -1399,12 +1428,12 @@
#if defined (__vax__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
- : "=g" ((USItype)(sh)), "=&g" ((USItype)(sl)) \
+ : "=g" (sh), "=&g" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
- : "=g" ((USItype)(sh)), "=&g" ((USItype)(sl)) \
+ : "=g" (sh), "=&g" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
#define smul_ppmm(xh, xl, m0, m1) \
@@ -1441,12 +1472,12 @@
#if defined (__z8000__) && W_TYPE_SIZE == 16
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
- : "=r" ((unsigned int)(sh)), "=&r" ((unsigned int)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((unsigned int)(ah)), "r" ((unsigned int)(bh)), \
"%1" ((unsigned int)(al)), "rQR" ((unsigned int)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
- : "=r" ((unsigned int)(sh)), "=&r" ((unsigned int)(sl)) \
+ : "=r" (sh), "=&r" (sl) \
: "0" ((unsigned int)(ah)), "r" ((unsigned int)(bh)), \
"1" ((unsigned int)(al)), "rQR" ((unsigned int)(bl)))
#define umul_ppmm(xh, xl, m0, m1) \
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