[PATCH] fix m32r target macros add_ssaaaa and sub_ddmmss in longlong.h

[Kazuhiro Inaoka]

Hello,

This is a longlong.h patch for a M32R target.

Please apply it.

Regards,

Kazuhiro Inaoka.

-------- Original Message --------
Subject: [PATCH] fix m32r-elf target macros add_ssaaaa and sub_ddmmss in 
longlong.h
Date: Wed, 28 May 2003 18:11:13 +0900
From: Kazuhiro Inaoka <inaoka.kazuhiro at renesas.com>
To: <gcc-patches at gcc.gnu.org>

  I found miss difinition macros add_ssaaaa() and sub_ddmmss() for M32R
target in longlong.h.

2003-05-28 Kazuhiro Inaoka <inaoka dot kazuhiro at renesas dot com>
     * gcc/longlong.h: Fix macros for m32r add_ssaaaa and sub_ddmmss

*** longlong.h.org Wed May 28 18:17:00 2003
--- longlong.h Wed May 28 18:18:33 2003
*************** UDItype __umulsidi3 (USItype, USItype);
*** 381,387 ****
   #if defined (__M32R__) && W_TYPE_SIZE == 32
   #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
     /* The cmp clears the condition bit.  */ \
!   __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0"   \
       : "=r" ((USItype) (sh)),     \
         "=&r" ((USItype) (sl))     \
       : "%0" ((USItype) (ah)),     \
--- 381,387 ----
   #if defined (__M32R__) && W_TYPE_SIZE == 32
   #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
     /* The cmp clears the condition bit.  */ \
!   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %3,%0"   \
       : "=r" ((USItype) (sh)),     \
         "=&r" ((USItype) (sl))     \
       : "%0" ((USItype) (ah)),     \
*************** UDItype __umulsidi3 (USItype, USItype);
*** 391,397 ****
       : "cbit")
   #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
     /* The cmp clears the condition bit.  */ \
!   __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0"   \
       : "=r" ((USItype) (sh)),     \
         "=&r" ((USItype) (sl))     \
       : "0" ((USItype) (ah)),     \
--- 391,397 ----
       : "cbit")
   #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
     /* The cmp clears the condition bit.  */ \
!   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"   \
       : "=r" ((USItype) (sh)),     \
         "=&r" ((USItype) (sl))     \
       : "0" ((USItype) (ah)),     \